論文

査読有り
2015年9月1日

Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier

IEEE Embedded Systems Letters
  • Ghada Abozaid
  • ,
  • Arnaud Tisserand
  • ,
  • Ahmed El-Mahdy
  • ,
  • Yasutaka Wada

7
3
開始ページ
77
終了ページ
80
記述言語
英語
掲載種別
研究論文(学術雑誌)
DOI
10.1109/LES.2015.2436372
出版者・発行元
Institute of Electrical and Electronics Engineers Inc.

The integration of fully homomorphic encryption (FHE) into embedded systems is limited due to its huge computational requirements. FHE requires multiplications of operands up to millions of bits. Current implementations use high-end and parallel processors, leading to high-power consumption. We propose a hardware-software system to benefit from the best of hardware (performance/low-power) and software (flexibility) capabilities. In this letter, we present our first codesign results for hardware dedicated multiplication units, which is used as atomic operations by the software layer. We report FPGA implementation results for those units and software performance estimations of their use in multiplications up to 16 millions-bit operands. In range of 10 W power consumption, our analysis show that good FHE performance is affordable.

リンク情報
DOI
https://doi.org/10.1109/LES.2015.2436372
ID情報
  • DOI : 10.1109/LES.2015.2436372
  • ISSN : 1943-0663
  • SCOPUS ID : 84940992781

エクスポート
BibTeX RIS