MOCHIZUKI Akira

J-GLOBAL         Last updated: Nov 2, 2012 at 20:16
 
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Name
MOCHIZUKI Akira
Affiliation
Tohoku University
Section
Center for Spintronics Integrated Systems
Degree
Ph. D.(Tohoku University)

Research Areas

 
 

Academic & Professional Experience

 
Apr 1995
 - 
Sep 2002
Engineer, Dept. Development of RISC CPU IPs for ASIC, NEC
 
Oct 2002
 - 
Mar 2007
Research Associate(Assistant Professor), Research Institute of Electrical Communication, Tohoku University
 
Apr 2007
 - 
Mar 2010
Renesas Technology Corp, Engineer, Development of a new CPU for embedded systems
 
Apr 2010
 - 
Oct 2012
Engineer, Dept. Development of platforms including CPU IPs, memories, buses and peripherals for MCUs(Micro-Controller Units), Renesas Electronics Corp.
 
Nov 2012
 - 
Today
Assistant Professor, Center for Spintronics Integrated Systems, Tohoku University
 

Education

 
Apr 1993
 - 
Mar 1995
Graduate School of Information Sciences, Tohoku University
 
 
 - 
Mar 1993
School of Engineering, Tohoku University
 

Committee Memberships

 
 
   
 
IEICE  member
 
 
   
 
IEEE  member
 

Awards & Honors

 
2005
Ando Incentive Prize for the Study of Electronics
 

Misc

 
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic
IEEE Int. Symp. on Multiple-Valued Logic   24 19-26   1994
A 1.5V-Supply 200MHz Pipelined Multiplier Using Multiple-Valued Current-Mode MOS Differntial Logic Circuits
Takahiro Hanyu, Akira Mochizuki and Michitaka Kameyama
International Solid-State Circuits Conference(ISSCC)   38 314-315   1995
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.
IEEE Int. Symp. on Multiple-Valued Logic   25 64-69   1995
IEE Proceeding -- Circuits Devices and Systems   143(6) 331-336   1996
Multiple-Valued Dynamic Source-Coupled Logic
Proceedings 33rd IEEE International Symposium on Multiple-Valued Logic   ,207-212    2003

Conference Activities & Talks

 
0.2V-Swing Multiple-Valued Differential-Pair Circuit and Its Application to Arithmetic VLSI
14th International Workshop on Post-Binary ULSI Systems   2005   

Association Memberships

 
 

Research Grants & Projects

 
Study on compensations of process variations and immunities of crosstalk noise
Project Year: 2003   
At the nano-order technology node, the behaviors of the same shape transistors in a chip are different. it is known that its error is a Process variation. Voltage and Temperature variation also cause malfunction on logic operations. Since the vari...
High-functional logic circuit using non-volatile storage devices
Project Year: 2003   
At a low-power chip, several techniques are utilized: clock-gating, lowing supply voltage, cutting off power supply for an inactive block, using multi-threshold transistors, and so on. It is important to reduce dynamic power as well as static powe...
Low-power technique using dynamic voltage/frequency scaling (DVFS) and task skipping
Project Year: 2003   
In order to design a low-power SAD unit in motion vector detector with keeping throughput, a combination of DVFS and task skipping method can be performed. It is well known that the DVFS technique makes it possible to reduce the total power of a c...
Intra-chip high-throughput communication method
Project Year: 2003   
To perform high-throughput network on a chip (NoC), many methods, ring, mesh, and cross-bar, have been reported for multi- or many-core system LSI which has a low-power highly-parallel capability. A common bus or a shared bus that is well known as...
High-performance VLSI based on multiple-valued logic
Project Year: 1993   
Due to demand on high-speed arithmetic operations on near-future VLSI, a combination of highly-parallel multiple-valued arithmetic algorithms, current-mode representation and switching operation of a source-coupled pair or a differential circuit e...

Patents

 
Register file and method for designing a register file
20040060015(US Patent Application)
Register file and method for the same
GB2394581(UK Patent)