MISC

2014年4月

Design and evaluation of a 67% area-less 64-bit parallel reconfigurable 6-input nonvolatile logic element using domain-wall motion devices

JAPANESE JOURNAL OF APPLIED PHYSICS
  • Daisuke Suzuki
  • ,
  • Masanori Natsui
  • ,
  • Akira Mochizuki
  • ,
  • Takahiro Hanyu

53
4
開始ページ
04EM03-1-04EM03-5
終了ページ
記述言語
英語
掲載種別
DOI
10.7567/JJAP.53.04EM03
出版者・発行元
IOP PUBLISHING LTD

A 6-input nonvolatile logic element (NV-LE) using domain-wall motion (DWM) devices is presented for low-power and real-time reconfigurable logic LSI applications. Because the write current path of a DWM device is separated from its read current path and the resistance value of the write current path is quite small, multiple DWM devices can be reprogrammed in parallel, thus affording real-time logic-function reconfiguration within a few nanoseconds. Moreover, by merging a circuit component between combinational and sequential logic functions, transistor counts can be minimized. As a result, 2-ns 64-bit-parallel circuit reconfiguration is realized by the proposed 6-input NV-LE with 67% lesser area than a conventional CMOS-based alternative, with a simulation program with integrated circuit emphasis (SPICE) simulation under a 90 nm CMOS/MTJ technologies. (C) 2014 The Japan Society of Applied Physics

リンク情報
DOI
https://doi.org/10.7567/JJAP.53.04EM03
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000338185100140&DestApp=WOS_CPL
ID情報
  • DOI : 10.7567/JJAP.53.04EM03
  • ISSN : 0021-4922
  • eISSN : 1347-4065
  • Web of Science ID : WOS:000338185100140

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