2006年
Highly reliable multiple-valued circuit based on dual-rail differential logic
Proceedings of The International Symposium on Multiple-Valued Logic
- ,
- 巻
- Vol.36
- 号
- CD-ROM
- 開始ページ
- 5
- 終了ページ
- 記述言語
- 英語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- DOI
- 10.1109/ISMVL.2006.24
A new multiple-valued circuit based on dual-rail differential logic is proposed for crosstalk noise reduction. Since a dual-rail complementary duplication is performed by using two differential-pair circuits (DPCs), noise effect is distributed to only one DPC, if common-mode, noise is applied to dual-rail input lines. The dual-rail complementary duplicated DPCs makes noise effect reduced, because one of the DPC makes error operation and the other makes no-error operation, so that the output noise level which is summed up of two DPCs becomes half. By using the Schmitt-trigger circuit, the half-level noise effect from two DPCs is almost eliminated. As a typical design example of arithmetic modules, it is discussed to implement a crosstalk-noise-free radix-2 signed-digit full adder in a 0.18μm CMOS technology at the supply voltage of 1.8V. © 2006 IEEE.
- ID情報
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- DOI : 10.1109/ISMVL.2006.24
- ISSN : 0195-623X
- SCOPUS ID : 33751068745