論文

2012年

A High-Throughput Pipelined Parallel Architecture for JPEG XR Encoding

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS
  • Hiroshi Tsutsui
  • ,
  • Koichi Hattori
  • ,
  • Hiroyuki Ochi
  • ,
  • Yukihiro Nakamura

11
4
開始ページ
Article No. 72
終了ページ
記述言語
英語
掲載種別
研究論文(学術雑誌)
DOI
10.1145/2362336.2362339
出版者・発行元
ASSOC COMPUTING MACHINERY

JPEG XR is an emerging image coding standard, based on HD Photo developed by Microsoft Corporation. It supports high compression performance twice as high as the de facto image coding system, namely, JPEG, and also has an advantage over JPEG 2000 in terms of computational cost. JPEG XR is expected to be widespread for many devices including embedded systems in the near future. In this article, we propose a novel architecture for JPEG XR encoding. In previous architectures, entropy coding was the throughput bottleneck because it was implemented as a sequential algorithm to handle data with dependency. We found that there is no dependency in intra-macroblock data, and we could safely pipeline all the encoding processes including the entropy coding. In addition, each module of our architecture, which can be regarded as a pipeline stage, can be parallelized. As a result, our architecture can achieve 12.8 pixel/cycle at its maximum. To demonstrate our architecture, we designed three versions of our architecture with different degrees of parallelism of one, two, and four. Our four-way parallel architecture achieves 579 Mpixel/sec at 181MHz clock frequency for grayscale images.

リンク情報
DOI
https://doi.org/10.1145/2362336.2362339
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000313395700003&DestApp=WOS_CPL
ID情報
  • DOI : 10.1145/2362336.2362339
  • ISSN : 1539-9087
  • Web of Science ID : WOS:000313395700003

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