論文

査読有り
2019年

部分再構成を用いたプロセッサの耐故障化手法に関する検討

電気学会論文誌. D, 産業応用部門誌
  • 荻堂 盛也
  • ,
  • 山田 親稔
  • ,
  • 宮城 桂
  • ,
  • 市川 周一
  • ,
  • 藤枝 直輝

139
2
開始ページ
187
終了ページ
192
記述言語
日本語
掲載種別
DOI
10.1541/ieejias.139.187
出版者・発行元
一般社団法人 電気学会

<p>In this paper, we propose a reconfigurable fault tolerant architecture that can recover from failure status with spare space. Recently, progress in semiconductor technology has been remarkable due to microfabrication of devices. The semiconductor technique plays an important role in artificial satellites and aircraft. Furthermore, it has guaranteed the reliability of the circuits by the multiplexing structure. However, in embedded systems, space-saving is regarded to be as important as reliability. In the traditional approach, the area overhead tends to become large. Reconfigurable fault tolerance can achieve high area efficiency. In this research, we aim to improve the reliability and area efficiency for a single stuck-at fault of the processor. In this article, we reproduce the proposed method using Tcl script and proposed standalone fault tolerant operation using embedded Linux.</p>

リンク情報
DOI
https://doi.org/10.1541/ieejias.139.187
CiNii Articles
http://ci.nii.ac.jp/naid/130007601534
CiNii Books
http://ci.nii.ac.jp/ncid/AN10012320
URL
http://id.ndl.go.jp/bib/029498182
ID情報
  • DOI : 10.1541/ieejias.139.187
  • ISSN : 0913-6339
  • CiNii Articles ID : 130007601534
  • CiNii Books ID : AN10012320

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