島宗 洋介

Integration strategy of embedded sige S/D CMOS from viewpoint of performance and cost for 45nm-node and beyond 

International Symposium on VLSI Technology, Systems, and Applications, Proceedings 124-125 2008年  

Novel stack-SIN gate dielectrics for high performance 30 nm CMOS for 45 nm node with uniaxial strained silicon 

Digest of Technical Papers - Symposium on VLSI Technology 176-177 2006年  

Silicon Self-Diffusion in Heavily B-Doped Si Using Highly Pure ³⁰Si Epitaxial Layer 

Proc. Int. Symp. Silicon Materials Science and Technology X (Edited by H. Huff, L. Fabry, D. Gilles, U. Goesele, T. Hattori, W. Huber, S. Ikeda, H. Iwai, P. Packan, H. Richter, M. Rodder, E. Weber and R. Wise, The Electrochem. Soc., Pennington, NJ, 2006) 2(2) 287-297 2006年  査読有り

Determination of diffusivities of Si self-diffusion and Si self-interstitials using isotopically enriched single-or multi-Si-30 epitaxial layers 

Semiconductor Defect Engineering-Materials, Synthetic Structures and Devices 864 425-436 2005年  査読有り

A highly robust SiGe source drain technology realized by disposable sidewall spacer (DSW) for 65nm node and beyond 

PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE 305-308 2005年  査読有り

Si self-diffusivity using isotopically pure Si-30 epitaxial layers 

MATERIALS SCIENCE AND ENGINEERING B-SOLID STATE MATERIALS FOR ADVANCED TECHNOLOGY 114 330-333 2004年12月  査読有り

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs 

Technical Digest - International Electron Devices Meeting, IEDM 209-212 2004年