Presentations

Oct 23, 2000

Memory Access Estimation of Filter Bank Implementation on Different DSP Architectures

Technical report of IEICE. DSP
  • MIZUTANI Naoki
  • ,
  • MURAMATSU Shogo
  • ,
  • KIKUCHI Hisakazu

Language
Japanese
Presentation type
Oral presentation (general)

In this report, supposing digital signal processors (DSP) of different architectures, the efficient implementation of filter banks is investigated. Especially, focusing on the memory accesses, the number of memory transfers, the power consumptions and the processing accuracies are discussed. DSP 〓mploys the Harvard architecture for fast signal processing and has special functional units, such as multiplier-and-accumulator (MAC) units, Barrel shifters and so forth. Even if looking only the MAC units, however, there are some differences in the number of units, the number of accumulators and so forth. In addition, the processing procedure influences the efficiency of memory accesses and the processing accuracy. It is known that the extra memory accesses affects the power consumption, and is very important problem. On the other hand, filter banks are known as an element technique of subband coding and wavelet coding. Thus, their efficient implementation is expected. In this report, firstly the unified representation of analyses and synthesis banks are introduced and then it is divided into two types of procedures. These procedures are investigated with MAC units of different architectures.

Link information
URL
http://ci.nii.ac.jp/naid/110003280338