In MPEG4, a new moving picture coding standard, there both 16×16 block mode and 8×8 block mode. In this report, we propose a linear array architecture of motion estimatior with 8×8 block mode. The proposed architecture is improved in both the internal of processing elements (PE) and comparator module from the conventional one. The input is the same as the conventional one. In the internal of PE, some multiplexers and an accumulater are added to the convetional architecture. The improvement of the conventional PE makes it possible to select and accumulate the sum of absolute differences (SAD) in the 8×8 block mode. Since the output timing of SAD in the 8×8 block mode differs from that of 16×16 block mode, This paper proposes two architecture for the 8×8 block mode. The verify the significance for VLSI implementation, the performance is estimated by using the synthesis result of the VHDL.