Takayuki Mori

Profile Information

Affiliation: Assistant Professor, College of Engineering Department of Electrical and Electronic Engineering, Kanazawa Institute of Technology

Degree: Doctor of Engineering(Kanazawa Institute of Technology)

ORCID iD: https://orcid.org/0000-0002-9199-0868
J-GLOBAL ID: 202001003944567955
researchmap Member ID: R000011662

Research Interests

Research History

Apr, 2023 - Present

Assistant Professor, College of Engineering Department of Electrical and Electronic Engineering, Kanazawa Institute of Technology
Apr, 2017 - Mar, 2023

Researcher, Center for Electric, Optic and Energy (EOE) Applications, Kanazawa Institute of Technology
Apr, 2014 - Mar, 2017

Toshiba Corporation Storage & Electronic Devices Solutions Company (Current Kioxia Corporation)

Education

Apr, 2012 - Mar, 2014

Graduate Program in Electrical Engineering and Electronics, Graduate School of Engineering, Kanazawa Institute of Technology
Apr, 2010 - Mar, 2012

Department of Electrical and Electronic Engineering, College of Engineering, Kanazawa Institute of Technology

Committee Memberships

Nov, 2020 - Present

Technical Program Committee, International Conference on Microelectronic Test Structures (ICMTS)

Papers

Steep Subthreshold Slope Gate-Controlled Carrier-Injection SOI Transistor for Ultralow Power Applications

Haruki Yonezaki, Takayuki Mori, Jiro Ida

IEEE Journal of the Electron Devices Society, 2025 Peer-reviewed
Neural Encoder Using “PN-Body Tied SOI-FET”

Masaki Kobayashi, Jiro Ida, Takayuki Mori

2024 IEEE Silicon Nanoelectronics Workshop (SNW), 12 107-108, Jun 15, 2024 Peer-reviewed
Steep Slope Device “N-type Gate-Controlled Carrier-Injection SOI-Transistor”: Suppression of Hysteresis by Ar-ion Implantation and Possibility of CMOS

Haruki Yonezaki, Takayuki Mori, Jiro Ida

2024 IEEE Silicon Nanoelectronics Workshop (SNW), 479 57-58, Jun 15, 2024 Peer-reviewed
Back Bias Effect with Hysteresis in Cryogenic 200 nm SOI MOSFETs

Ryusei Ri, Takayuki Mori, Hiroshi Oka, Takahiro Mori, Jiro Ida

10th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS) 2024, May 17, 2024 Peer-reviewed
Control of Hysteresis and Latch-Up on Steep Switching “PN-Body Tied SOI-FET Diode” by Ar-Ion Implantation

Hiroyoshi Matsushita, Takayuki Mori, Jiro Ida

2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), Apr 22, 2024 Peer-reviewed
New Steep Subthreshold Slope Device “Gate-Controlled Carrier-Injection SOI-Transistor”

Haruki Yonezaki, Takayuki Mori, Jiro Ida

2024 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Mar 3, 2024 Peer-reviewed
Leaky-integrate-and-fire operation with signal amplification using gate-controlled carrier-injection silicon-on-insulator transistor

Haruki Yonezaki, Takayuki Mori, Jiro Ida

Japanese Journal of Applied Physics, 63(2) 02SP83-02SP83, Feb 1, 2024 Peer-reviewed
Neural Network Modeling of Steep Turn-on Diodes: Validation and Implementation in SPICE Simulations

Kengo Nakata, Takayuki Mori, Jiro Ida

2023 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK), Nov 16, 2023 Peer-reviewed
Integrate-and-Fire Operation with Signal Amplification by using “Dual-Gate PN-Body Tied SOI-FET”

Haruki Yonezaki, Takayuki Mori, Jiro Ida

Extended Abstracts of the 2023 International Conference on Solid State Devices and Materials, Sep 7, 2023 Peer-reviewed
Steep Subthreshold Slope “Dual-Gate PN-Body Tied SOI-FET” -First Fabrication Results-

Haruki Yonezaki, Takayuki Mori, Jiro Ida

Solid-State Electronics, 108720-108720, Jul, 2023 Peer-reviewed
First fabrication results of Steep Subthreshold Slope "Dual-Gate PN-Body Tied SOI-FET"

Haruki Yonezaki, Takayuki Mori, Jiro Ida

9th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS) 2023, May 12, 2023 Peer-reviewed
Neuronal Function and Signal Amplification Device with Steep Switching “PN-Body Tied SOI-FET”

Takayuki Mori, Jiro Ida

2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), Apr 17, 2023 Peer-reviewedLead authorCorresponding author
Variability Evaluation of MOS-gated PNPN Diode for Hardware Spiking Neural Network

Toshihiro Takada, Takayuki Mori, Jiro Ida

2023 35th International Conference on Microelectronic Test Structure (ICMTS), Mar 27, 2023 Peer-reviewed
Sharp Turn-on Diode by Steep SS “PN-Body Tied SOI FET” for Ultra-low Power RF Energy Harvesting

Masayuki Ono, Jiro Ida, Takayuki Mori, Koichiro Ishibashi

2023 7th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Mar 7, 2023 Peer-reviewed
Modeling of Super Steep Subthreshold Slope Device by using Neural Network

Kengo Nakata, Takayuki Mori, Jiro Ida

2022 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK), Nov 28, 2022 Peer-reviewed
Evaluation of Multi-Finger PN-Body Tied SOI-FET-Origin and Suppression of Stepped I_d–V_g Characteristics-

Takayuki Mori, Kengo Nakata, Jiro Ida

2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Apr 18, 2022 Peer-reviewedLead authorCorresponding author
Neuron Function with Single Device by using "PN-Body Tied SOI-FET"-Mimicking Leaky Integrate and Fire Characteristics-

Toru Sasaki, Takayuki Mori, Jiro Ida

2022 6th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Mar 6, 2022 Peer-reviewed
RF Evaluation of Steep Subthreshold Slope “PN-Body Tied SOI-FET”

Mitsuhiro Yuizono, Jiro Ida, Takayuki Mori, Koichiro Ishibashi

2021 IEEE International Meeting for Future Electron Devices, Kansai (IMFEDK), Nov 17, 2021 Peer-reviewed
Developing Ultralow Trun-on Voltage Diode by Steep Slope "PN-Body Tied SOI-FET"

Masayuki Ono, Jiro Ida, Takayuki Mori, Koichiro Ishibashi

2021 IEEE International Meeting for Future Electron Devices, Kansai (IMFEDK), Nov 17, 2021 Peer-reviewed
Investigation of capacitor-less integrate and fire neuron by using dual-gate a PN-body tied silicon on insulator field-effect transistor

Takayuki Mori, Jiro Ida

Japanese Journal of Applied Physics, 60(SB) SBBA04-SBBA04, May 1, 2021 Peer-reviewedLead authorCorresponding author

Misc.

極低電圧動作を狙ったSteep SS "Dual-Gate型PN-Body Tied SOI-FET"試作結果—Evaluation of Steep Subthreshold Slope Device "Dual-Gate type PN-Body Tied SOI-FET" for Ultra Low Voltage Operation—情報センシング

米崎晴貴, 井田次郎, 森貴之, 石橋孝一郎

映像情報メディア学会技術報告 = ITE technical report, 46(23) 19-22, Aug, 2022
招待講演極低電力LSIに向けたSteep Slope "PN-Body Tied SOI-FET"の研究状況—Research Status of Steep Slope "PN-Body Tied SOI-FET" for Ultra low Power LSI Applications—情報センシング

井田次郎, 森貴之

映像情報メディア学会技術報告 = ITE technical report, 46(23) 15-18, Aug, 2022
Neuron Circuit Using Dual Gate PN Body-Tied SOI-FET

Mori Takayuki, Ida Jiro

JSAP Annual Meetings Extended Abstracts, 2021.1 2346-2346, Feb 26, 2021
Analysis of Saturation Effect at Low Vds appearing in PN-Body Tied SOI-FET

Ito Hiroki, Ida Jiro, Mori Takayuki

JSAP Annual Meetings Extended Abstracts, 2020.2 1839-1839, Aug 26, 2020
急峻なSSを持つ"PN-Body Tied SOI-FET"のCMOSインバータ伝達特性

イシグロショウタ, イダジロウ, モリタカユキ, イシバシコウイチロウ

44(17) 57-60, Aug, 2020
Application of Neuromorphic Using PN Body-Tied SOI-FET

Mori Takayuki, Ida Jiro, Endo Hiroki, Sasaki Toru

JSAP Annual Meetings Extended Abstracts, 2020.1 3654-3654, Feb 28, 2020
Analysis of Drain Current Enhancement Effect on PN-Body Tied SOI-FET -Comparison of Bulk vs Surface Conduction-

Ito Hiroki, Ida Jiro, Mori Takayuki

JSAP Annual Meetings Extended Abstracts, 2020.1 2714-2714, Feb 28, 2020
RFエネルギーハーベスティング用のSOI-MOSダイオードと高インピーダンスアンテナを用いたレクテナの検討と試作

河野渓介, 井田次郎, 森貴之, 野口啓介, 伊東健治

電気・情報関係学会北陸支部連合大会(CD-ROM), 2020, 2020
Proposal of New Structure PN-Body-Tied SOI-FET for Leakage Current Reduction

Mori Takayuki, Ida Jiro, Endo Hiroki

JSAP Annual Meetings Extended Abstracts, 2019.2 3115-3115, Sep 4, 2019
Data of "PN-Body-Tied SOI-FET" manufactured using 65 nm thin BOX FDSOI

Daimatsu Keita, Ida Jiro, Yamada Takuya, Mori Takayuki

JSAP Annual Meetings Extended Abstracts, 2019.2 3114-3114, Sep 4, 2019
急峻なSSを持つ"PN Body-Tied SOI-FET"におけるBOX中の正電荷と基板バイアスの影響

ヤブキワタル, イダジロウ, モリタカユキ, イシバシコウイチロウ, アライヤスオ

119(162) 89-93, Aug, 2019
極急峻SSを持つ"PN-Body Tied SOI-FET"を使った極低電力レクテナ

ヤマダタクヤ, イダジロウ, モリタカユキ, ヤスマルノブヒコ, イトウケンジ, イシバシコウイチロウ

119(161) 95-98, Aug, 2019
nW級1MHz帯レクテナ

ヤスマルノブヒコ, ナカニシカント, イトウケンジ, ツチモトシュンヤ, ヤマダタクヤ, モリタカユキ, イダジロウ

119(12) 39-43, Apr 22, 2019
Transient Analysis by using TCAD on Super-Steep SS “PN-Body-Tied SOI-FET”

Mori Takayuki, Ida Jiro, Endo Hiroki

JSAP Annual Meetings Extended Abstracts, 2019.1 2816-2816, Feb 25, 2019
招待講演急峻なSSを持つPN-Body Tied SOI-FETを用いたMOS Diode接続での特性および微小電圧整流実験

モモセシュン, イダジロウ, ヤマダタクヤ, モリタカユキ, イトウケンジ, イシバシコウイチロウ, アライヤスオ

118(291) 59-64, Nov, 2018
Transient characterization with pulse measurement on Super Steep SS PN-Body Tied SOI FET

Endo Hiroki, Ida Jiro, Mori Takayuki, Nakano Shunichi, Yabuki Wataru

JSAP Annual Meetings Extended Abstracts, 2018.2 2948-2948, Sep 5, 2018
Effect of Substrate Bias on P/N-Channel Super-Steep SS PN-Body-Tied SOI-FET

Yabuki Wataru, Ida Jiro, Mori Takayuki, Endo Hiroki, Nakano Syunichi

JSAP Annual Meetings Extended Abstracts, 2018.2 2947-2947, Sep 5, 2018
急峻なSSを持つ"PN-Body Tied SOI-FET"を使った極低電圧整流実験

モモセシュン, イダジロウ, ヤマダタクヤ, モリタカユキ, イトウケンジ, イシバシコウイチロウ, アライヤスオ

118(173) 31-34, Aug, 2018
Analysis of Super-Steep SS PN-Body-Tied SOI FET by TCAD Simulation

Mori Takayuki, Ida Jiro

JSAP Annual Meetings Extended Abstracts, 2018.1 280-280, Mar 5, 2018
Characterization of Hysteresis on Super Steep SS PN-Body Tied FET

Inoue Shota, Jiro Ida, Takayuki Mori, Takahiro Yoshida

JSAP Annual Meetings Extended Abstracts, 2017.2 2973-2973, Aug 25, 2017

Professional Memberships

Jan, 2023 - Present

IEEE
Oct, 2017 - Present

The Institute of Electronics, Information and Communication Engineers
Sep, 2017 - Present

The Japan Society of Applied Physics

Research Projects

A study on fan-in/fan-out augmentation of neuron circuits using a novel device

Grants-in-Aid for Scientific Research Grant-in-Aid for Early-Career Scientists, Grant-in-Aid for Early-Career Scientists, Japan Society for the Promotion of Science, Apr, 2021 - Mar, 2026
Double Gate PN-Body Tied SOI-FETを用いた低消費電力ニューロン回路の研究開発

KIOXIA Corporation, Jul, 2020 - Mar, 2021
新構造”PN-Body Tied SOI-FET”を用いた低消費電力ニューロン回路の研究開発

KIOXIA Corporation, Jan, 2019 - Mar, 2020

Industrial Property Rights

特開2021-028943 半導体構造および半導体構造の制御方法

井田次郎, 森貴之

Profile Information

Research Interests

Research History

Education

Committee Memberships

Papers

Misc.

Professional Memberships

Research Projects

Industrial Property Rights

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