Tohru Mogami

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Name
Tohru Mogami
E-mail
t-mogamipetra-jp.org
Affiliation
NEC Corporation

Research Interests

 
 

Published Papers

 
Tsuyoshi Horikawa, Tsuyoshi Horikawa, Daisuke Shimura, Tohru Mogami
MRS Communications   1-7   Jan 2016
Copyright © Materials Research Society 2016 Low-propagation-loss silicon wire waveguides are key components of optical integrated circuits. In this paper, we clarified, through assessment of the relationship between waveguide loss and fabrication ...
Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita, Hironori Sasaki, Ken Morito, Kazuhiko Kurata
Microelectronic Engineering      Jun 2015
© 2015. The Si photonics platform for 300mm SOI wafers has been built up for optical multi-applications. The performance of main optical waveguide devices has been demonstrated. State-of-the-art propagation loss values are obtained for optical wav...
TAKAYA Satoshi, BANDO Yoji, OHKAWA Toru, TAKARAMOTO Toshiharu, YAMADA Toshio, SOUDA Masaaki, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto
IEICE Trans. Electron.   96(6) 884-893   Jun 2013
The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel si...
Inoue Koji, Takamizawa Hisashi, Shimizu Yasuo, Yano Fumiko, Toyama Takeshi, Nishida Akio, Mogami Tohru, Kitamoto Katsuyuki, Miyagi Takahiro, Kato Jun, Akahori Seishi, Okada Noriyuki, Kato Mikio, Uchida Hiroshi, Nagai Yasuyoshi
Applied Physics Express   6(4) 46502-046502-4   Apr 2013
Three-dimensional dopant distributions in actual n- and p-channel metal--oxide--semiconductor devices of 65 nm node in two kinds of commercially available products were investigated by atom probe tomography (APT). Detailed and quantitative dopant ...
Terada Kazuo, Takeda Ryo, Tsuji Katsuhiro, Tsunomura Takaaki, Nishida Akio, Mogami Tohru
Jpn J Appl Phys   51(9) 94301-094301-4   Sep 2012
The effect of the channel dopant non-uniformity on metal--oxide--semiconductor field-effect transistor (MOSFET) transconductance variability is studied using the simple current model and the test MOSFETs having various channel width and length. It...
H. Takamizawa, Y. Shimizu, K. Inoue, T. Toyama, F. Yano, A. Nishida, T. Mogami, N. Okada, M. Kato, H. Uchida, K. Kitamoto, K. Kitamoto, T. Miyagi, J. Kato, Y. Nagai
Applied Physics Letters   100    Jun 2012
The correlation between threshold voltage (V T) and channel boron concentration in silicon-based 65 nm node negative-type metal-oxide- semiconductor field-effect transistors was studied by atom probe tomography (APT). V T values were determined fo...
Kazuo Terada, Kazuhiko Sanai, Katsuhiro Tsuji, Takaaki Tsunomura, Akio Nishida, Tohru Mogami
Solid-State Electronics   69 62-66   Mar 2012
The effect of the dopant uniformity in an MOSFET channel on the threshold voltage variability is studied with a simple model and the test MOSFET array which includes many MOSFETs with different channel length and width. The simple model shows that...
Yoji Bando,Satoshi Takaya,Toru Ohkawa,Toshiharu Takaramoto,Toshio Yamada,Masaaki Souda,Shigetaka Kumashiro,Tohru Mogami,Makoto Nagata
IEICE Transactions   95-C(1) 137-145   2012   [Refereed]
H. Takamizawa, Y. Shimizu, K. Inoue, T. Toyama, N. Okada, M. Kato, H. Uchida, F. Yano, A. Nishida, T. Mogami, Y. Nagai
Applied Physics Letters   99    Sep 2011
The greater variability in the electrical properties of n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) compared with those of p-type MOSFETs poses problems for scaling of silicon based large-scale integration technology. We ha...
Toshiro Hiramoto, Toshiro Hiramoto, Makoto Suzuki, Xiaowei Song, Ken Shimizu, Takuya Saraya, Akio Nishida, Takaaki Tsunomura, Shiro Kamohara, Kiyoshi Takeuchi, Tohru Mogami
IEEE Transactions on Electron Devices   58 2249-2256   Aug 2011
Noise margin, characteristics of six individual cell transistors, and their variability in static random-access memory (SRAM) cells are directly measured using a special device-matrix-array test element group of 16-kb SRAM cells, and the correlati...
Ono Shiano, Yamane Miyuki, Okushima Hirohisa, Koguchi Masanari, Shinada Hiroyuki, Kakibayashi Hiroshi, Yano Fumiko, Tsunomura Takaaki, Nishida Akio, Mogami Tohru
Applied Physics Express   4(6) 66601-066601-3   Jun 2011
To clarify the origin of on-state drain current (I_{\text{ON}}) variability in metal--oxide--semiconductor field-effect transistors (MOSFETs), we applied three-dimensional scanning transmission electron microscopy (3D STEM) observation to two tran...
Y. Shimizu, H. Takamizawa, K. Inoue, K. Inoue, T. Toyama, Y. Nagai, N. Okada, M. Kato, H. Uchida, F. Yano, T. Tsunomura, A. Nishida, T. Mogami
Applied Physics Letters   98    Jun 2011
Coimplantation of heterogeneous dopants in materials can be used to control the principal dopant distribution. We used atom probe tomography (APT) and secondary ion mass spectrometry (SIMS) to investigate the impact of coimplanted carbon on boron ...
Atsushi Hiraiwa, Akio Nishida, Akio Nishida, Tohru Mogami
IEEE Transactions on Electron Devices   58 1672-1680   Jun 2011
The authors propose a model of line-edge and line-width roughness (LER and LWR) of actual device patterns, which received some smoothing steps, for accurate estimation of device variability. The model assumes that LER/LWR has originally an exponen...
Tsunomura Takaaki, Kumar Anil, Mizutani Tomoko, Nishida Akio, Takeuchi Kiyoshi, Inaba Satoshi, Kamohara Shiro, Terada Kazuo, Hiramoto Toshiro, Mogami Tohru
Jpn J Appl Phys   50(4) 04DC08-04DC08-5   Apr 2011
The properties of drain current variability in field-effect transistors (FETs) at high temperature are experimentally investigated. It is found that the on-state drain current (Tex) at high temperature has a strong correlation with $I_...
Takamizawa Hisashi, Inoue Koji, Shimizu Yasuo, Toyama Takeshi, Yano Fumiko, Tsunomura Takaaki, Nishida Akio, Mogami Tohru, Nagai Yasuyoshi
Applied Physics Express   4(3) 36601-036601-3   Mar 2011
Randomness of channel dopant distribution in metal--oxide--semiconductor field-effect transistor (MOSFET) structures was analyzed by laser-assisted atom probe tomography. Three-dimensional dopant distributions of boron and arsenic atoms in MOSFET ...
Masaaki Souda,Yoji Bando,Satoshi Takaya,Toru Ohkawa,Toshiharu Takaramoto,Toshio Yamada,Shigetaka Kumashiro,Tohru Mogami,Makoto Nagata
IEICE Transactions   94-C(6) 1024-1031   2011   [Refereed]
Yoji Bando,Satoshi Takaya,Toru Ohkawa,Toshiharu Takaramoto,Toshio Yamada,Masaaki Souda,Shigetaka Kumashiro,Tohru Mogami,Makoto Nagata
IEICE Transactions   94-C(4) 495-503   2011   [Refereed]
Tsunomura Takaaki, Kumar Anil, Mizutani Tomoko, Nishida Akio, Takeuchi Kiyoshi, Inaba Satoshi, Kamohara Shiro, Terada Kazuo, Hiramoto Toshiro, Mogami Tohru
Applied Physics Express   3(11) 114201-114201-3   Nov 2010
The origin of larger on-state drain current (Tex) variability in n-type field-effect transistors (NFETs) than that in p-type field-effect transistors (PFETs), is investigated by evaluating FETs fabricated using 65 nm technology. It is ...
Toshiaki Tsuchiya, Yuki Mori, Yuta Morimura, Tohru Mogami, Yuzuru Ohji
Jpn J Appl Phys   49(6) 64001-064001-5   Jun 2010
Fluctuations in not only the number but also the individual electronic properties of interface traps in small-gate-area metal–oxide–semiconductor field-effect transistors (MOSFETs) containing just a few interface traps have been directly observed....
Hitoshi Wakabayashi, Hitoshi Wakabayashi, Tatsuya Ezaki, Tatsuya Ezaki, Toshitsugu Sakamoto, Hisao Kawaura, Nobuyuki Ikarashi, Nobuyuki Ikezawa, Mitsuru Narihiro, Yukinori Ochiai, Yukinori Ochiai, Takeo Ikezawa, Kiyoshi Takeuchi, Toyoji Yamamoto, Masami Hane, Masami Hane, Tohru Mogami, Tohru Mogami
IEEE Transactions on Electron Devices   53 1961-1968   Sep 2006
Sub-10-nm planar bulk CMOS devices were demonstrated by a lateral source/drain (S/D) junction control, which consists of the notched gate electrode, shallow S/D extensions, and steep halo in a reverse-order S/D formation. Furthermore, the transpor...
Takakuni Douseki, Masashi Yonemaru, Eiji Ikuta, Akira Matsuzawa, Atsushi Kameyama, Shunsuke Baba, Tohru Mogami, Hakaru Kyuragi
IEICE Transactions on Electronics   E87-C 437-447   Apr 2004
This paper describes an ultralow-power multi-threshold (MT) CMOS/SOI circuit technique that mainly uses fully-depleted MOSFETs. The MTCMOS/SOI circuit, which combines fully-depleted low-and medium-Vth CMOS/SOI logic gates and high-Vth power-switch...
Akira Tanabe, Yasushi Nakahara, Akio Furukawa, Tohru Mogami
IEEE Journal of Solid-State Circuits   38 107-113   Jan 2003
A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the mul...
Mitsuhiro Togo, Koji Watanabe, Toyoji Yamamoto, Nobuyuki Ikarashi, Toru Tatsumi, Haruhiko Ono, Tohru Mogami
IEEE Transactions on Electron Devices   49 1903-1909   Nov 2002
We have developed a low-leakage and highly reliable 1.5-nm SiON gate-dielectric by using radical oxygen and nitrogen. In this development, we introduce a new method for determining an ultrathin SiON gate-dielectric thickness based on the threshold...
Mitsuhiro Togo, Koji Watanabe, Masayuki Terai, Toyoji Yamamoto, Toshinobu Fukai, Toru Tatsumi, Tohru Mogami, Tohru Mogami
IEEE Transactions on Electron Devices   49 1736-1741   Oct 2002
We have demonstrated that oxynitridation using radical-oxygen (radical-O) and radical-nitrogen (radical-N) improves reverse narrow channel effects (RNCE) and reliability in a sub-1.5-nm-thick gate-SiO2 FETs with narrow channel and shallow-trench i...
Mitsuhiro Togo, Koji Watanabe, Masayuki Terai, Shigeru Kimura, Toyoji Yamamoto, Toru Tatsumi, Tohru Mogami, Tohru Mogami
IEEE Transactions on Electron Devices   49 1761-1767   Oct 2002
We will report the importance of oxynitridation using radical-oxygen and -nitrogen to form a low-leakage and highly reliable 1.6-nm SiON gate-dielectric without performance degradation in n/pFETs. It was found that oxidation using radical-oxygen f...
Jong Wook Lee, Jong Wook Lee, Yukisige Saitoh, Risho Koh, Tohru Mogami
IEEE Electron Device Letters   23 467-469   Aug 2002
New device isolation process, called elevated field insulator (ELFIN) process, for ultrathin SOI devices with top silicon film less than 20 nm has been proposed and successfully demonstrated. In ELFIN process, gate oxidation and subsequent gate po...
Mitsuhiro Togo, Shigeru Kimura, Tohru Mogami, Tohru Mogami
IEEE Transactions on Electron Devices   49 1165-1171   Jul 2002
We have developed high-quality 1.5-nm-SiON gate dielectrics using recoiled-oxygen-free processing. We found that oxygen recoiling from a sacrificial oxide during ion implantation or defects induced by recoiled oxygen change the growth mechanism of...
WAKABAYASHI Hitoshi, ANDOH Takeshi, MOGAMI Tohru, TATSUMI Toru, KUNIO Takemitsu
IEICE transactions on electronics   85(5) 1104-1110   May 2002
A uniform raised-salicide technology has been investigated using both uniform selective-epitaxial-growth (SEG) silicon and salicide films, to reduce a junction leakage current of shallow source/drain (S/D) regions for high-performance CMOS devices...
Hitoshi Wakabayashi, Hitoshi Wakabayashi, Toyoji Yamamoto, Kazuyoshi Yoshida, Eiichi Soda, Ken Ichi Tokunaga, Tohru Mogami, Tohru Mogami, Takemitsu Kunio, Takemitsu Kunio
IEEE Transactions on Electron Devices   49 295-300   Feb 2002
Advanced tungsten/pn-poly-Si gate CMOS devices with an ultralow sheet resistance of 1 Ω/sq. have been demonstrated using an amorphous-Si/TiN buffer layer. A low-resistivity tungsten film is formed by a large grain size of tungsten on an amorphous-...
Hitoshi Wakabayashi, Hitoshi Wakabayashi, Makoto Ueki, Mitsuru Narihiro, Toshinori Fukai, Nobuyuki Ikezawa, Tomoko Matsuda, Kazuyoshi Yoshida, Kazuyoshi Yoshida, Kiyoshi Takeuchi, Yukinori Ochiai, Tohru Mogami, Tohru Mogami, Takemitsu Kunio, Takemitsu Kunio, Takemitsu Kunio
IEEE Transactions on Electron Devices   49 89-95   Jan 2002
Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 μA/μm...
Koji Watanabe, Toru Tatsumi, Mitsuhiro Togo, Tohru Mogami
Journal of Applied Physics   90 4701-4707   Nov 2001
We studied nitrogen incorporation in ultrathin oxynitride films by using oxygen and nitrogen radicals, and investigated the dependence of the electrical properties on the nitrogen profile. We found that the nitrogen position in the films could be ...
Hitoshi Wakabayashi, Hitoshi Wakabayashi, Yukishige Saito, Kiyoshi Takeuchi, Tohru Mogami, Tohru Mogami, Takemitsu Kunio, Takemitsu Kunio
IEEE Transactions on Electron Devices   48 2363-2369   Oct 2001
A novel dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film is described. It is based on a new finding that threshold voltage (V th) depends on the concentration of nitrogen in the TiNx gate electrode. We found that a...
Kiyoshi Takeuchi, Risho Koh, Tohru Mogami, Tohru Mogami
IEEE Transactions on Electron Devices   48 1995-2001   Sep 2001
This paper addresses the scalability of bulk CMOS, and the feasibility of intrinsic channel SOI (IC-SOI) CMOS, as an alternative to the bulk, in view of the threshold voltage (VTH) fluctuations. The impact of dopant-induced VTH variations on bulk ...
Mitsuru Narihiro, Hitoshi Wakabayashi, Makoto Ueki, Kohichi Arai, Takashi Ogura, Yukinori Ochiai, Tohru Mogami
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers   39(12) 6843-6848   Dec 2000
To increase the throughput of electron beam lithography used to fabricate sub-100-nm patterns, we developed an electron beam and deep UV intra-level mix-and-match lithography process, that uses the JBX-9300FS point-electron-beam system and a conve...
H. Takemura, H. Ohki, H. Nakazawa, Y. Nakagawa, M. Isobe, Y. Ochiai, T. Ogura, M. Narihiro, T. Mogami
Microelectronic Engineering   53 329-332   Jun 2000
New electron beam lithography system, JBX-9300FS, was developed and evaluated. This system features a spot beam, vector beam-scanning system, and step and repeats stage. Minimum beam diameter is 4nm at 100kV and 7nm at 50kV. The beam scanning syst...
Yukinori Ochiai, Takashi Ogura, Tohru Mogami
Microelectronic Engineering   46 187-190   May 1999
We have developed a 100-kV point electron-beam (EB) system for the fabrication of sub-0.1-μm MOS devices on 8-inch wafers and x-ray masks. The calculated beam diameter is less than 4 nm at 100 kV and 7 nm at 50 kV. The EB system has a large deflec...
Risho Koh, Risho Koh, Tohru Mogami, Tohru Mogami, Haruo Kato, Haruo Kato
IEICE Transactions on Electronics   E80-C 893-897   Dec 1997
Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2 m fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multi...
Masanori Izumikawa, Masanori Izumikawa, Hiroyuki Igura, Hiroyuki Igura, Koichiro Furuta, Hiroshi Ito, Hitoshi Wakabayashi, Ken Nakajima, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina, Masakazu Yamashina
IEEE Journal of Solid-State Circuits   32 52-60   Jan 1997
This paper describes a 0.25-μm CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-μm CMOS technology,...
Kazuo Terada, Tohru Mogami
Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)   80 11-17   Jan 1997
A test circuit in which many MOSFETs of identical structure are parallel connected is proposed for measuring the standard deviation of MOSFET threshold voltage. The threshold voltage, which is extracted from the drain-current versus gate-voltage (...
Tohru Mogami, Hitoshi Wakabayashi, Yukishige Saito, Toru Tatsumi, Takeo Matsuki, Takemitsu Kunio
IEEE Transactions on Electron Devices   43 932-939   Dec 1996
A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent preaworphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and unifor...
TERADA Kazuo, MOGAMI Toru
The transactions of the Institute of Electronics, Information and Communication Engineers   79(11) 691-697   Nov 1996
大量の同一構造MOSFETを並列接続したテスト回路を用いて,しきい値電圧の標準偏差を簡単に測定する方法を提案している.このテスト回路を一つのMOSFETとみなし,そのドレーン電流とゲート電圧の関係からしきい値電圧を抽出すると,その値は同回路に含まれるすべてのMOSFETのしきい値電圧の平均値よりも標準偏差に関係した量だけ異なる値を示す.このことを利用すると,MOSFETのしきい値電圧標準偏差を簡単に測定することができる.本論文はその測定原理,単体MOSFETを用いたその実験的確認,そして精...
Mogami Tohru, Johansson Lars E. G., Sakai Isami, Fukuma Masao
IEICE transactions on electronics   78(3) 255-260   Mar 1995
Surface-channel PMOSFETs are suitable for use in the quarter micron CMOS devices. For surface-channel PMOSFETs with p^+ poly-Si gates, boron penetration and hot-carrier effects were investigated. When the annealing temperature is higher and the ga...
R. Koh, T. Mogami
IEEE Electron Device Letters   15 327-329   Jan 1994
The carrier recombination influence on the floating body effect for fully depleted n-channel SOIMOSFET was analyzed by device simulation. It was found that the hole diffusion to the source electrode is negligibly small and that the surface recombi...
T. Mogami, H. Okabayashi, A. Tanikawa, E. Nagasawa
Nuclear Inst. and Methods in Physics Research, B   39 500-503   Mar 1989
The calculated maximum aspect ratio (depth-to-diameter ratio) for via-hole filling without cavity creation by bias-sputtering, considering the shadowing effect, was found to be in good agreement with the experimental value, which was practically l...
MOGAMI Tohru, OKABAYASHI Hidekazu, MORIMOTO Mitsutaka
Japanese journal of applied physics. Pt. 1, Regular papers & short notes   27(8) 1516-1520   Aug 1988
Via-hole filling and surface planarization (planarized via-hole filling) were achieved by molybdenum (Mo) bias sputtering under high (〜80%) resputtering, i.e., high (〜 -600 V) substrate bias voltage, conditions. It was shown that Mo redeposition o...
Tohru Mogami, Hidekazu Okabayashi, Mitsutaka Morimoto
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers   27(8) 1516-1520   Aug 1988
Via-hole filling and surface planarization (planarized via-hole filling) were achieved by molybdenum (Mo) bias sputtering under high (approximately 80%) resputtering, i.e., high (approximately -600 v) substrate bias voltage, conditions. It was sho...
T. Mogami, H. Okabayashi, E. Nagasawa, M. Morimoto
17-23   Dec 1985
Planarized via-hole filling properties and limitations, using RF bias sputtering, have been investigated. It was found that planarized via-hole filling with molybdenum (Mo) was accomplished for via-holes with a lower than 0. 6 aspect ratio under -...

Misc

 
FUJIKATA Junichi, OHASHI Keishi, MOGAMI Toru
Japanese journal of optics   40(2) 98-103   Feb 2011
OHASHI Keishi, TORII Sunao, MOGAMI Tohru
The Journal of the Institute of Electronics, Information, and Communication Engineers   93(11) 933-937   Nov 2010
LSIのグローバル配線における消費電力,シグナルインテグリティ等の課題を解決するために光配線を導入する検討を行った.Siフォトニクス,表面プラズモンなどの光技術により,寸法的にはLSI内の機能ブロック間を光配線で結ぶことができ,また配線遅延が低減することを示すことができる.ここでは,最新の光配線技術に基づき光配線のアーキテクチャについて考察した内容を報告する.
MOGAMI Tohru, SUGA Osamu, MORI Ichiro
應用物理   78(8) 765-773   Aug 2009
Takayasu Sakurai, Akira Matsuzawa, Takakuni Douseki, Takakuni Douseki, Hideaki Matsuhashi, Toshiaki Tsuchiya, Yasuhisa Omura, Hiroshi Shimomura, Masashi Yonemaru, Koji Fujii, Atsushi Kameyama, Hiroshi Kawaguchi, Tsuneo Tsukahara, Minoru Kozaki, Masayoshi Kinoshita, Akihiro Sawada, Yasuyuki Matsuya, Jun Terada, Yoshitsugu Inagaki, Tsuneaki Fuse, Yusuke Ohtomo, Hiroshi Koizumi, Shunsuke Baba, Kazuyoshi Nishimura, Yoshifumi Yoshida, Norio Hama, Tohru Mogami, Toshiro Hiramoto, Ken Uchida, Shin Ichi Takagi, Toshinori Numata
Fully-Depleted SOI CMOS Circuits and Technology: For Ultralow-Power Applications   1-411   Dec 2006
The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have ...
最上 徹
Electronic journal   (148) 84-86   Jul 2006
OHSHIMA Shigetoshi, MOGAMI Toru, KUNII Makoto, WAKIYAMA Tokuo
OYOBUTURI   54(3) 252-259   1985
An apparatus for scanning-laser annealing with a CW CO2 laser was designed and constructed. Scanning-laser annealing applied to amorphous V-Si sputtered films caused a structural change to the A 15 V3Si phase with a Tc onset at 15 K. Superconducti...

Books etc

 
桜井 貴康, Matsuzawa Akira, Douseki Takakuni
Springer   ISBN:0387292187

Conference Activities & Talks

 
田中 有, 最上 徹
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   29 Oct 2015   
Tsuyoshi Horikawa, Tsuyoshi Horikawa, Tohru Mogami
IEEE International Conference on Group IV Photonics GFP   23 Oct 2015   
© 2015 IEEE. The dimension control technology for silicon photonics devices based on 40-nm-node CMOS technology are reviewed. By using ArF immersion lithography in the fabrication technology, the high-level reproducihility in resonant wavelength o...
Tsuyoslii Horikawa, Tsuyoslii Horikawa, Tohru Mogami
IEEE International Conference on Group IV Photonics GFP   23 Oct 2015   
© 2015 IEEE. The dimension control technology for silicon photonics devices based on 40-nm-node CMOS technology are reviewed. By using ArF immersion lithography in the fabrication technology, the high-level reproducihility in resonant wavelength o...
Horikawa Tsuyoshi, Mogami Tohru
Proceedings of the Society Conference of IEICE   25 Aug 2015   
Horikawa Tsuyoshi, Shimura Daisuke, Jeong Seok-Hwan, Tokushima Masatoshi, Mogami Tohru
Proceedings of the Society Conference of IEICE   9 Sep 2014   
Daisuke Shimura, Tsuyoshi Horikawa, Hideaki Okayama, Seok Hwan Jeong, Masatoshi Tokushima, Hironori Sasaki, Tohru Mogami
IEEE International Conference on Group IV Photonics GFP   1 Jan 2014   
© 2014 IEEE. World-record low propagation losses for single-mode silicon waveguides with TE-polarization were demonstrated. As the results of precise width control, the deviation of 1.8nm was confirmed for the resonance peaks of a ring-resonator o...
Hideyuki Nakamura, Hideyuki Nakamura, Taiki Uemura, Taiki Uemura, Kan Takeuchi, Kan Takeuchi, Toshikazu Fukuda, Toshikazu Fukuda, Shigetaka Kumashiro, Shigetaka Kumashiro, Tohru Mogami, Tohru Mogami
IEEE International Reliability Physics Symposium Proceedings   28 Sep 2012   
Neutron induced single event transient (SET) has been measured on NAND and inverter (INV) chain with changing fan-out, drive strength, size of drain diffusion area, temperature and VDD on 40nm and 90nm bulk CMOS technology. As the pulse width dist...
Kazuo Terada, Ryo Takeda, Katsuhiro Tsuji, Takaaki Tsunomura, Akio Nishida, Tohru Mogami
IEEE International Conference on Microelectronic Test Structures   24 May 2012   
The effect of Device Matrix Array structure on MOSFET g m- variability measurement is studied. One of the two transfer gates, which are connected to an MOSFET source terminal for both Kelvin measurement and addressable access, is removed. This mod...
Katsuhiro Tsuji, Kazuo Terada, Ryo Takeda, Takaaki Tsunomura, Akio Nishida, Tohru Mogami
IEEE International Conference on Microelectronic Test Structures   24 May 2012   
The threshold voltage variations for the MOSFETs having various channel structures are evaluated from their measured capacitance-voltage (C-V) curves. It is found that they show reasonable dependence on the channel structure and smaller than those...
Takaya Satoshi, Bando Yoji, Ohkawa Toru, Takaramoto Toshiharu, Yamada Toshio, Souda Masaaki, Kumashiro Shigetaka, Mogami Tohru, Nagata Makoto
Proceedings of the IEICE General Conference   6 Mar 2012   
Hironori Sakamoto,Shigetaka Kumashiro,Shigeo Sato,Naoki Wakita,Tohru Mogami
Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012   2012   
Kiyoshi Takeuchi, Akio Nishida, Shiro Kamohara, Toshiro Hiramoto, Tohru Mogami
Digest of Technical Papers - Symposium on VLSI Technology   16 Sep 2011   
It is shown, using kinetic Monte Carlo simulation, that variability in the amount of point defects created by source/drain (S/D) implantation can significantly increase NFET random fluctuation through the modulation of boron transient enhanced dif...
T. Tsunomura, J. Nishimura, A. Kumar, A. Nishida, S. Inaba, K. Takeuchi, T. Hiramoto, T. Hiramoto, T. Mogami
Digest of Technical Papers - Symposium on VLSI Technology   16 Sep 2011   
VT variability degradation induced by negative bias temperature instability (NBTI) and its relation with random dopant fluctuation (RDF) are investigated by a special large-scale (16000 PFETs) device matrix array (DMA) TEG exclusive for NBTI varia...
Kazuo Terada, Kazuhiko Sanai, Katsuhiro Tsuji, Takaaki Tsunomura, Akio Nishida, Tohru Mogami
IEEE International Conference on Microelectronic Test Structures   9 Sep 2011   
The dopant uniformity in an MOSFET channel is estimated using the test MOSFET array which includes many MOSFETs with different channel length. Takeuchi coefficient as a function of the channel length is calculated from the measured threshold volta...
Katsuhiro Tsuji, Kazuo Terada, Ryota Kikuchi, Takaaki Tsunomura, Akio Nishida, Tohru Mogami
IEEE International Conference on Microelectronic Test Structures   9 Sep 2011   
Test structure for charge-based capacitance measurement (CBCM) is improved, to achieve higher accuracy of measuring capacitance-voltage (C-V) curves for actual size MOSFETs. Capacitance mismatch between the device under test (DUT) and the referenc...
Tohru Mogami
Extended Abstracts of the 11th International Workshop on Junction Technology, IWJT 2011   1 Sep 2011   
CMOS scaling has been a basic power of LSI development for higher performance, higher packing density and lower cost. For device scaling-down, size miniaturization has been one of the important issues to fabricate fine devices. Furthermore, normal...
MIZUTANI Tomoko, KUMAR Anil, NISHIDA Akio, TAKEUCHI Kiyoshi, INABA Satoshi, KAMOHARA Shiro, TERADA Kazuo, MOGAMI Tohru, HIRAMOTO Toshiro
Technical report of IEICE. SDM   18 Aug 2011   
VTH variability in high-k/metal-gate (HKMG) MOSFETs are evaluated using Takeuchi plot and compared with that in SiON MOSFETs for the first time. Parameters needed for Takeuchi plot is extracted from C-V measurement. It is found that, although VTH ...
KUMAR Anil, MIZUTANI Tomoko, NISHIDA Akio, TAKEUCHI Kiyoshi, INABA Satoshi, KAMOHARA Shiro, TERADA Kazuo, MOGAMI Tohru, HIRAMOTO Toshiro
Technical report of IEICE. SDM   18 Aug 2011   
This paper presents the statistical analysis of a newly found drain current variability component called "current-onset voltage" (COV) variability as well as DIBL variability in CMOS devices. 3D device simulation based results show that al-though ...
TAKAYA Satoshi, BANDO Yoji, OHKAWA Toru, SOUDA Masaaki, TAKARAMOTO Toshiharu, YAMADA Toshio, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto
Technical report of IEICE. ICD   14 Jul 2011   
Substrate noise sensitivity of an analog circuit consists of the sensitivity of a device and noise propagation from the noise source to the target circuit. It is necessary for substrate noise coupling analysis to consider the physical layout of th...
Bando Yoji, Takaya Satoshi, Hasegawa Takashi, Ohkawa Toru, Takaramoto Toshiharu, Yamada Toshio, Souda Masaaki, Kumashiro Shigetaka, Mogami Tohru, Nagata Makoto
Proceedings of the IEICE General Conference   28 Feb 2011   
Song X., Suzuki M., Saraya T., Nishida A., Tsunomura T., Kamohara S., Takeuchi K., Inaba S., Mogami T., Hiramoto T.
Technical report of IEICE. SDM   24 Jan 2011   
The static noise margin (SNM) as well as V_<th>, gm, body factor, and drain-induced-barrier-lowering (DIBL) in individual transistors in SRAM cells are directly measured by 16k bit device-matrix-array (DMA) SRAM TEG. It is found that, besides V_<t...
Satoshi Takaya,Yoji Bando,Toru Ohkawa,Toshiharu Takaramoto,Toshio Yamada,Masaaki Souda,Shigetaka Kumashiro,Tohru Mogami,Makoto Nagata
Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, California, USA, 14-16 March 2011   2011   
T. Hiramoto, T. Hiramoto, T. Mizutani, A. Kumar, A. Nishida, T. Tsunomura, S. Inaba, K. Takeuchi, S. Kamohara, T. Mogami
Proceedings - IEEE International SOI Conference   30 Dec 2010   
Intrinsic channel SOI MOSFETs were fabricated and their variability were compared with conventional bulk MOSFETs. It is found for the first time that, besides VTH variability, both DIBL variabitlity and current-onset voltage variability are well s...
X. Song, M. Suzuki, T. Saraya, A. Nishida, T. Tsunomura, S. Kamohara, K. Takeuchi, S. Inaba, T. Mogami, T. Hiramoto, T. Hiramoto
Technical Digest - International Electron Devices Meeting, IEDM   1 Dec 2010   
The static noise margin (SNM) as well as Vth, gm, body factor, and drain-induced-barrier-lowering (DIBL) in individual transistors in SRAM cells are directly measured by 16k bit device-matrix-array (DMA) SRAM TEG. It is found that, besides Vth var...
Masaaki Soda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010   1 Dec 2010   
A sine-wave noise generator with a harmonic-eliminated waveform is proposed for measuring the noise tolerance of analog IPs. In the waveform, harmonics up to the thirteenth harmonic are eliminated by combining seven rectangular waves with 22.5-deg...
OHASHI Keishi, MOGAMI Tohru
Technical report of IEICE. ICD   22 Nov 2010   
On-chip optical interconnection is expected to give an answer to the problems on signal integrity and data band width. Cost and foot print size issues associated with the optical technology have been improved by introducing silicon photonics and n...
TAKAYA Satoshi, BANDO Yoji, HASEGAWA Takashi, OHKAWA Toru, SOUDA Masaaki, TAKARAMOTO Toshiharu, YAMADA Toshio, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto
Technical report of IEICE. ICD   22 Nov 2010   
Measure substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 32 different geometory and operating conditions. Substrate sensitivity has a relation with the signal gain, and the output resistance value of the t...
TANAKA Katsuhiko, NAKAMURA Hideyuki, UEMURA Taiki, TAKEUCHI Kan, FUKUDA Toshikazu, KUMASHIRO Shigetaka, MOGAMI Tohru
Technical report of IEICE. SDM   4 Nov 2010   
Soft errors in logic circuits due to the propagation of erroneous signal caused by ionized particle generated by cosmic neutrons, which is called Single Event Transient (SET), might degrade reliability of future LSIs. A calculation model for estim...
T. Tsunomura, A. Kumar, T. Mizutani, C. Lee, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, T. Hiramoto, T. Mogami
Digest of Technical Papers - Symposium on VLSI Technology   19 Oct 2010   
Causes of drain current local variability are analyzed by decomposing into current variability components. Besides VTH and Gm components, it is newly found that effects of "current onset" variability caused by channel potential fluctuations largel...
Hiramoto Toshiro, Suzuki Makoto, Saraya Takuya, Shimizu Ken, Nishida Akio, Kamohara Shiro, Takeuchi Kiyoshi, Mogami Tohru
Technical report of IEICE. SDM   19 Aug 2010   
A special device-matrix-array (DMA) TEG of 16k bit SRAM cells has been designed. Static noise margins (SNM) and 6 transistors in cells are directly measured and their fluctuations are examined. It is found for the first time that one-side SNM foll...
MIZUTANI Tomoko, TSUNOMURA Takaaki, KUMAR Anil, NISHIDA Akio, TAKEUCHI Kiyoshi, INABA Satoshi, KAMOHARA Shiro, TERADA Kazuo, MOGAMI Tohru, HIRAMOTO Toshiro
Technical report of IEICE. SDM   19 Aug 2010   
It is revealed that drain current variability is fluctuated by "current-onset voltage" as well as threshold voltage V_<TH> and transconductance G_m. Device-matrix-array (DMA) TEG with 8k transistors fabricated by the 65nm technology is measured. M...
Hiramoto Toshiro, Suzuki Makoto, Saraya Takuya, Shimizu Ken, Nishida Akio, Kamohara Shiro, Takeuchi Kiyoshi, Mogami Tohru
Technical report of IEICE. ICD   19 Aug 2010   
A special device-matrix-array (DMA) TEG of 16k bit SRAM cells has been designed. Static noise margins (SNM) and 6 transistors in cells are directly measured and their fluctuations are examined. It is found for the first time that one-side SNM foll...
MIZUTANI Tomoko, TSUNOMURA Takaaki, KUMAR Anil, NISHIDA Akio, TAKEUCHI Kiyoshi, INABA Satoshi, KAMOHARA Shiro, TERADA Kazuo, MOGAMI Tohru, HIRAMOTO Toshiro
Technical report of IEICE. ICD   19 Aug 2010   
It is revealed that drain current variability is fluctuated by "current-onset voltage" as well as threshold voltage V_<TH> and transconductance G_m. Device-matrix-array (DMA) TEG with 8k transistors fabricated by the 65nm technology is measured. M...
Takamizawa H., Shimizu Y., Nagai Y., Toyama T., Inoue K., Yano F., Tsunomura T., Nishida A., Mogami T.
Meeting abstracts of the Physical Society of Japan   18 Aug 2010   
BANDO Yoji, TAKAYA Satoshi, HASEGAWA Takashi, OHKAWA Toru, SOUDA Masaaki, TAKARAMOTO Toshiharu, YAMADA Toshio, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto
ITE Technical Report   22 Jul 2010   
In-situ DC measurements of individual transistors in a differential pair of an analog amplifier derive threshold voltage, V_<th>, of 1.0V transistors in a 90nm CMOS technology. On-chip continuous time waveform monitoring is used to evaluate AC res...
BANDO Yoji, TAKAYA Satoshi, HASEGAWA Takashi, OHKAWA Toru, SOUDA Masaaki, TAKARAMOTO Toshiharu, YAMADA Toshio, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto
Technical report of IEICE. ICD   15 Jul 2010   
In-situ DC measurements of individual transistors in a differential pair of an analog amplifier derive threshold voltage, V_<th>, of 1.0 V transistors in a 90 nm CMOS technology. On-chip continuous time waveform monitoring is used to evaluate AC r...
Tohru Mogami
Proceedings of SPIE - The International Society for Optical Engineering   14 Jul 2010   
In Si-LSI industry, the variation of device characteristics has been one of the issues because of 10-year-lifetime LSI and high-yield mass production, and it has been continuously developing the several methods to mitigate and straighten out it. C...
Toshiaki Tsuchiya, Yuki Mori, Yuta Morimura, Tohru Mogami, Yuzuru Ohji
ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference   1 Dec 2009   
Fluctuations in not only the number but also the individual carrier capture rate of interface traps in small gate-area MOSFETs containing only less than several interface traps have been investigated from an understanding of newly observed transie...
T. Tsunomura, A. Nishida, F. Yano, A. T. Putra, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Mama, T. Hiramoto, T. Hiramoto, T. Mogami
Digest of Technical Papers - Symposium on VLSI Technology   16 Nov 2009   
Extra VT variability sources in NMOS are investigated using Takeuchi plot. It is clearly shown that VT variation of boron channel NMOS cannot be explained solely by the channel depth profiles. Moreover it is clarified that boron TED is the dominan...
T. Tsunomura, A. Nishida, F. Yano, A. T. Putra, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, T. Hiramoto, T. Mogami
Digest of Technical Papers - Symposium on VLSI Technology   23 Sep 2008   
Using 1M DMA-TEG, the analyses of 5σ Vth fluctuation in 65nm-MOSFETs were carried out. Physical and electrical analyses confirmed that random dopant fluctuation is dominant though NMOSFET has larger fluctuation as compared with PMOSFET. To explain...
Tohru Mogami
ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings   2 Aug 2007   
Sub-10nm CMOS devices are the critical issue, because CMOS scaling is going to be sub-25nm regime. Scaling issues of nano-size MOSFETs can be discussed on the basis of sub-10 nm MOSFETs characteristics, which have been developed and confirmed swit...
H. Wakabayashi, T. Tatsumi, N. Ikarashi, M. Oshida, H. Kawamoto, N. Ikezawa, T. Ikezawa, T. Yamamoto, M. Hane, Y. Mochizuki, T. Mogami
Technical Digest - International Electron Devices Meeting, IEDM   1 Dec 2005   
Improved sub-10-nm CMOS devices have been investigated by the elevated source/drain extensions (eSDE) using the tunneling silicon selective epitaxial growth (Si-SEG) in the reverse-order source/drain formation. In this eSDE technology, the SEG-Si ...
Hitoshi Wakabayashi, Tatsuya Ezaki, Toyoji Yamamoto, Masami Hane, Tohru Mogami
Proceedings - Electrochemical Society   1 Dec 2005   
We discuss the sub-10-nm planar-bulk-CMOS devices achieved by a lateral source/drain (S/D) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SDE) and steep halo.Direct-tunneling currents between sourc...
Tohru Mogami
Proceedings - Electrochemical Society   1 Dec 2004   
Ultra-small MOSFET device design, High-k gate-stacked devices and Low-k/Cu interconnects are described from the viewpoint of process modules of scaled ULSIs. Sub-10nm planar bulk-CMOS devices were demonstrated by the strict impurity profile contro...
Hitoshi Wakabayashi, Tatsuya Ezaki, Masami Hane, Takeo Ikezawa, Toshitsugu Sakamoto, Hisao Kawaura, Shigeharu Yamagami, Nobuyuki Ikarashi, Kiyoshi Takeuchi, Toyoji Yamamoto, Tohru Mogami
Technical Digest - International Electron Devices Meeting, IEDM   1 Dec 2004   
Transport properties of sub-10-nm planar bulk MOS-FETs have been evaluated. Direct-tunneling currents between source and drain (S/D) regions with not only the gate-length effects but also "drain-induced tunneling modulation (DITM)" effects are cle...
M. Togo, T. Fukai, Y. Nakahara, S. Koyama, M. Makabe, E. Hasegawa, M. Nagase, T. Matsuda, K. Sakamoto, S. Fujiwara, Y. Goto, T. Yamamoto, T. Mogami, M. Ikeda, Y. Yamagata, K. Imai
Digest of Technical Papers - Symposium on VLSI Technology   1 Oct 2004   
We have developed a power-aware CMOS technology featuring variable V DD and back-bias control. Three typical operation modes are defined: high-speed mode (VDD=1.2V, VB=0V), nominal mode (V DD=0.9V, VB=-0.5V) and power-save mode (V DD=0.6V, VB=-2.0...
Togo M., Fukai T., Nakahara Y., Koyama S., Makabe M., Hasegawa E., Nagase M., Matsuda T., Sakamoto K., Fujiwara S., Goto Y., Yamamoto T., Mogami T., Yamagata Y., Imai K.
Technical report of IEICE. SDM   13 Aug 2004   
We have developed a power-aware CMOS technology featuring variable V_<DD> and back-bias control. Three typical operation modes are defined: high-speed mode (V_<DD>=1.2V, V_B=0V), nominal mode (V_<DD>=0.9V, V_B=-0.5V) and power-save mode (V_<DD>=0....
Toshiyuki Iwamoto, Takashi Ogura, Masayuki Terai, Hirohito Watanabe, Heiji Watanabe, Nobuyuki Ikarashi, Makoto Miyamura, Toru Tatsumi, Motofumi Saitoh, Ayuka Morioka, Koji Watanabe, Yukishige Saito, Yuko Yabe, Taeko Ikarashi, Koji Masuzaki, Yasunori Mochizuki, Tohru Mogami
Technical Digest - International Electron Devices Meeting   1 Dec 2003   
For 90 nm node poly-Si gated MISFETs with HfSiO(1.8nm) insulator, a nearly symmetrical set of Vth's for NFET and PFET: (0.38V and -0.46V, respectively) have been realized for low power device operation. The key technology is the suppression of Vth...
Hitoshi Wakabayashi, Shigeharu Yamagami, Nobuyuki Ikezawa, Atsushi Ogura, Mitsuru Narihiro, Koh Ichi Arai, Yukinori Ochiai, Kiyoshi Takeuchi, Toyoji Yamamoto, Tohru Mogami
Technical Digest - International Electron Devices Meeting   1 Dec 2003   
Sub-10-nm planar-bulk-CMOS devices were clearly demonstrated by a lateral source/drain (S/D) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SDE) and steep halo. Good cut-off characteristics were ob...
Ayuka Morioka, Hirohito Watanabe, Makoto Miyamura, Toru Tatsumi, Motohumi Saitoh, Takashi Ogura, Toshiyuki Iwamoto, Taeko Ikarashi, Yukishige Saito, Yuko Okada, Heiji Watanabe, Yasunori Mochiduki, Tohru Mogami
Digest of Technical Papers - Symposium on VLSI Technology   1 Oct 2003   
MISFETs with HfSiO (EOT: 1.8 nm) gate insulator have been reached high Ion (95%) and low gate leakage current (1/100) against SiO2 gate film. This was achieved by the suppression of the remote coulomb scattering, caused by the electron traps in th...
WAKABAYASHI Hitoshi, TAKEUCHI Kiyoshi, YAMAMOTO Toyoji, MOGAMI Tohru
Technical report of IEICE. SDM   15 Aug 2003   
Sub-50-nm CMOS devices are demonstrated using a steep halo, which is formed by high-ramp-rate spike annealing (HRR-SA) and reverse-order S/D (R-S/D) formation. For an off current less than 300 nA/μm, 24/33-nm n/pMOSFETs have high drive currents of...
LEE Jong-Wook, SAITOH Yukisige, KOH Risho, YAMAGAMI Shigeharu, WAKABAYASHI Hitoshi, MOGAMI Tohru
Technical report of IEICE. SDM   24 Jun 2002   
ELFIN (ELevated Field INsulator) process for device isolation and SEP (S/D Elevated by Poly-Si Plugging) process for elevated S/D structure is developed for ultra-thin SOI MOSFETs with SOI film less than 20 nm. With ELFIN, reverse narrow channel e...
LEE Jong-Wook, SAITOH Yukisige, KOH Risho, YAMAGAMI Shigeharu, WAKABAYASHI Hitoshi, MOGAMI Tohru
IEICE technical report. Electron devices   24 Jun 2002   
ELFIN (ELevated Field INsulator) process for device isolation and SEP (S/D Elevated by Poly-Si Plugging) process for elevated S/D structure is developed for ultra-thin SOI MOSFETs with SOI film less than 20 nm. With ELFIN, reverse narrow channel e...
Togo Mitsuhiro, Mogami Tohru
Technical report of IEICE. SDM   13 Jun 2002   
We have clarified effect of recoiled-oxygen on quality and growth mechanism of 1.5 nm SiON gate-dielectrics. In less than 2 nm SiON gate-dielectrics, oxygen recoiling from a sacrificial oxide during ion-implantation or defect induced by recoiled o...
Koh R, Takeuchi K, Mogami T
Proceedings of the IEICE General Conference   7 Mar 2002   
TAKEUCHI Kiyoshi, MOGAMI Tohru
Technical report of IEICE. SDM   15 Jan 2002   
For scaled low voltage CMOS, V_<TH>, V_<DD> and T_<OX> must be highly optimized to achieve both low power and high speed. To perform such optimization for complex system-on-a-chip's (SoCs) consisting of multiple blocks, and using multiple V_<TH>, ...
Togo Mitsuhiro, Watanabe Koji, Terat Masayuki, Fukai Toshinori, Narihiro Mitsuru, Aari Koichi, Yamamoto Toyoji, Tatsumi Toru, Mogami Tohru
Technical report of IEICE. SDM   14 Jan 2002   
We have demonstrated that radical oxynitridation improves reverse narrow channel effects (RNCE) and reliability in a sub-1.5 nm-thick gate-SiO_2 FETs with narrow channel and shallow-trench isolation (STI), which is suitable for high-density SRAM a...
Jong Wook Lee, Hisashi Takemura, Yukisige Saitoh, Risho Koh, Shigeharu Yamagami, Tohru Mogami, Mitsuyoshi Uto, Nobuyuki Ikezawa, Nobuyuki Takasu
IEEE Symposium on VLSI Circuits, Digest of Technical Papers   1 Jan 2002   
ELFIN (ELevated Field INsulator) process for device isolation and SEP (Source/Drain Elevated by Poly-Si Plugging) process for elevated S/D structure is developed for ultra-thin SOI MOSFETs with SOI film less than 20 nm. With ELFIN process, gate el...
Kazuya Uejima, Toyoji Yamamoto, Tohru Mogami
IEEE Symposium on VLSI Circuits, Digest of Technical Papers   1 Jan 2002   
We have developed a design for a polycrystalline (poly-) gate to be used in high performance sub-100 nm CMOS devices. The inversion capacitance (Cinv) in a device with poly-gate was found to obviously decrease as the gate length becomes shorter in...
Kiyoshi Takeuchi, Tohru Mogami
Technical Digest - International Electron Devices Meeting   1 Dec 2001   
A simple method for determining the optimal use of multiple transistor parameters (MP), i.e. multiple VTH, VDD, and TOX, for System-on-a-Chip's (SoC's) is proposed. Reasonable optimization results are automatically obtained for various SoC configu...
M. Togo, K. Watanabe, M. Terai, T. Fukai, M. Narihiro, K. Arai, S. Koyama, N. Ikezawa, T. Tatsumi, T. Mogami
Technical Digest - International Electron Devices Meeting   1 Dec 2001   
We have demonstrated that oxynitridation using radical-O and -N improves reserves narrow channel effects (RNCE) and reliability in a sub-1.5 nm-thick gate-SiO2 FETs with narrow channel and shallow-trench isolation (STI), which is suitable for high...
KOH Risho, TAKEMURA Hisashi, TAKEUCHI Kiyoshi, MOGAMI Tohru
Extended abstracts of the ... Conference on Solid State Devices and Materials   25 Sep 2001   
Togo Mitsuhiro, Watanabe Koji, Yamamoto Toyoji, Ikarashi Nobuyuki, Tatsumi Tohru, Ono Haruhiko, Mogami Tohru
Technical report of IEICE. SDM   8 Mar 2001   
We have developed a low-leakage and highly reliable 1.5 nm SiON gate dielectric by using radical oxynitridation. It was found that radical oxidation followed by radical nitridation provides 1.5 nm thick SiON in which leakage current is two orders ...
Koh Risho, Takemura Hisashi, Takeuchi Kiyoshi, Mogami Tohru
Technical report of IEICE. SDM   8 Mar 2001   
Since the electric field originated from the impurity ions are suppressed, a intrinsic- semiconductor-body SOI-MOSFET has a large carrier mobility and a possibility to enhance ON current. However, The Influence on the device miniaturization on the...
Tanabe Akira, Nakahara Yasushi, Furukawa Akio, Mogami Tohru
Proceedings of the IEICE General Conference   7 Mar 2001   
A. Tanabe, Y. Nakahara, A. Furukawa, T. Mogami
Digest of Technical Papers - IEEE International Solid-State Circuits Conference   1 Jan 2001   
A redundant multi-valued logic was proposed for 10Gb/s complementary metal oxide semiconductor (CMOS) quadrupole data rate demultiplexer integrated circuit (IC). The proposed architecture of a 1:4 demultiplexer IC redundant 3-valued logic consists...
M. Tada, H. Ohtake, Y. Harada, M. Hiroi, S. Saito, T. Onodera, N. Furutake, J. Kawahara, M. Tagami, K. Kinoshita, T. Fukai, T. Mogami, Y. Hayashi
IEEE Symposium on VLSI Circuits, Digest of Technical Papers   1 Jan 2001   
Barrier-metal-free (BMF), Cu dual-damascene interconnects (DDI) are fabricated in the plasma-polymerized, divinyl siloxane bis-benzocyclobutene (p-BCB: k=2.6) polymer film, which is featured by the anti-diffusive characteristics for the Cu. The BM...
M. Togo, K. Watanabe, M. Terai, S. Kimura, A. Morioka, T. Yamamoto, T. Tatsumi, T. Mogami
IEEE Symposium on VLSI Circuits, Digest of Technical Papers   1 Jan 2001   
We will report the importance of high-density base-SiO2 for nitridation, and demonstrate a low-leakage and highly reliable 1.6 nm gate-SiON without performance degradation in n/pFETs using the radical process. It was found that the high-density 1....
H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, T. Kunio
Technical Digest - International Electron Devices Meeting   1 Dec 2000   
45-nm CMOS devices with a steep halo using a high-ramp-rate spike annealing (HRR-SA) are demonstrated with drive currents of 697 and 292 μA/μm for an off current less than 10 nA/μm at 1.2 V. For an off current less than 300 nA/μm, 33-nm pMOSFETs h...
M. Tagami, T. Fukai, M. Hiroi, J. Kawahara, K. Shiba, M. Tada, T. Onodera, S. Saito, K. Kinoshita, T. Ogura, M. Narihiro, K. Arai, K. Yamaguchi, M. Fukaishi, K. Kikuta, T. Mogami, Y. Hayashi
Technical Digest - International Electron Devices Meeting   1 Dec 2000   
For high-speed CMOS devices, triple-layered Cu single damascene interconnects (SDI) with Cu-via plugs are fabricated in hybrid dielectric films of plasma-polymerized divinylsiloxan benzocyclobuten film (p-BCB: k=2.6) and p-CVD SiO2. No degradation...
K. Uejima, T. Yamamoto, T. Mogami
Technical Digest - International Electron Devices Meeting   1 Dec 2000   
We have developed highly reliable poly-SiGe-gated CMOS devices using a poly-SiGe/a-Si (3 nm) gate structure for sub-0.1μm CMOS devices. It was found that by adding a thin amorphous-Si (a-Si) layer, QBD(50%) is improved compared with the convention...
M. Togo, T. Mogami
Technical Digest - International Electron Devices Meeting   1 Dec 2000   
We have developed high-quality 1.5 nm SiON gate dielectrics using recoiled-oxygen-free processing. We found that oxygen recoiling from a sacrificial oxide during ion implantation or defects induced by recoiled oxygen change the growth mechanism of...
M. Mizuno, K. Anjo, Y. Sumi, H. Wakabayashi, T. Mogami, T. Horiuchi, M. Yamashina
Digest of Technical Papers - IEEE International Solid-State Circuits Conference   1 Dec 2000   
The transmission of clock signals on microstrip lines was considered. A 100mm 2 5GHz clocking network was used to overcome the obstacles which were responsible for the reduction of clock-skew. The voltage swings in the transmission line were reduc...
Koh Risho, Takeuchi Kiyoshi, Takemura Hisashi, Mogami Tohru
Technical report of IEICE. SDM   23 Nov 2000   
V_<th> sensitivities on the variation of L and T_<SOI> is simulated for a n-channel SOI-MOSFET of L=25nm and T_<SOI>=10nm. They were found that both sensitivities strongly depends on the substrate bias voltage, and that an optimum back bias voltag...
TAKEUCHI Kiyoshi, KOH Risho, MOGAMI Tohru
Extended abstracts of the ... Conference on Solid State Devices and Materials   28 Aug 2000   
Anjo K., Mizuno M., Sumi Y., Fukaishi M., Wakabayashi H., Mogami T., Horiuchi T., Yamashina M.
Technical report of IEICE. SDM   17 Aug 2000   
In this paper, clock distribution scheme with on-chip transmission lines is presented. This technique allows clock signals to be transmitted in electro-magnetic speed. This results in smaller clock skew because wire delay deviation caused by devic...
Koh Risho, Mogami Tohru
Technical report of IEICE. SDM   13 Mar 2000   
To enhance the performance of metal-oxide-silicon field-effect-transistors (MOSFETs), a new device having a Silicon-on-insulator (SOI) structure, called a striped-gate SOI-MOSFET, is proposed and its electrical characteristics are estimated by dev...
Anjo K., Masayuki M., Sumi Y., Wakabayashi H., Mogami T., Horiuchi T., Yamashina M.
Proceedings of the IEICE General Conference   7 Mar 2000   
M. Togo, K. Watanabe, T. Yamamoto, N. Ikarashi, K. Shiba, T. Tatsumi, H. Ono, T. Mogami
Digest of Technical Papers - Symposium on VLSI Technology   1 Jan 2000   
We have developed a low-leakage and highly-reliable 1.5 nm SiON gate-dielectric by using radical oxynitridation. In this development, we introduce a new method for determining ultra-thin SiON gate-dielectric thickness based on the threshold voltag...
H. Wakabayashi, T. Yamamoto, Y. Saito, T. Ogura, M. Narihiro, K. Tsuji, T. Fukai, K. Uejima, Y. Nakahara, K. Takeuchi, Y. Ochiai, T. Mogami, T. Kunio
Digest of Technical Papers - Symposium on VLSI Technology   1 Dec 1999   
A 0.10-μm CMOS device for system LSI was successfully integrated with a 40-nm gate sidewall (SW) using local-channel structure, offset spacer, highly-doped source/drain extensions (SDE), deep pocket, shallow source /drain (S/D) with 7-Ω/□ CoSi2 an...
K. Tsuji, K. Takeuchi, T. Mogami
Digest of Technical Papers - Symposium on VLSI Technology   1 Dec 1999   
It is demonstrated that low temperature activation of the source/drain impurity, induced by the re-crystallization of an amorphous substrate layer, is effective for realizing scaled CMOS with abrupt junction profiles. Physical 50-nm gate length pF...
N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, T. Horiuchi
Digest of Technical Papers - Symposium on VLSI Technology   1 Dec 1999   
This paper presents a new reliability scaling scenario for the CMOS devices with direct-tunneling ultra-thin gate oxide. Device degradation due to bias temperature instability (BTI) was studied. First, the stress voltage dependence of BTI results ...
Hitoshi Wakabayashi, Yukishige Saito, Kiyoshi Takeuchi, Tohru Mogami, Takemitsu Kunio
Technical Digest - International Electron Devices Meeting   1 Dec 1999   
A W/TiN metal gate CMOS technology is newly proposed using a nitrogen-concentration-controlled TiNx film. This is based on a new finding that the threshold voltage of a TiNx gate MOSFET depends on the nitrogen concentration in the TiNx film. The t...
M. Togo, T. Mogami, R. Kubota, H. Nobusawa, M. Hamada, K. Inoue, K. Mikagi, K. Yoshida, E. Soda, S. Kishi, K. Satou, T. Yamamoto, K. Takeda, Y. Aimoto, Y. Nakazawa, et al
Technical Digest - International Electron Devices Meeting   1 Dec 1999   
We have demonstrated three key integration technologies of thermally stable dual-gate CMOSFETs for DRAM-embedded ASICs. These technologies include: (1) a thermally stable W-polycide gate for every MOSFET and CoSi 2 diffusion for logic CMOS to main...
YAMAMOTO Toyoji, UEJIMA Kazuya, MOGAMI Tohru
Extended abstracts of the ... Conference on Solid State Devices and Materials   20 Sep 1999   
Koichi Ishida, Hitoshi Wakabayashi, Tohru Mogami
Materials Research Society Symposium - Proceedings   1 Dec 1998   
The mechanism of the narrow line effect in TiSi2 films on highly As-doped diffusion layers is studied by TEM observation of grains in the TiSi2. The narrow line effect is shown to be due to an enlargement of the TiSi2 grain size caused by regrowth...
Hitoshi Wakabayashi, Toyoji Yamamoto, Kazuyoshi Yoshida, Eiichi Soda, Ken ichi Tokunaga, Tohru Mogami, Takemitsu Kunio
Technical Digest - International Electron Devices Meeting   1 Dec 1998   
Advanced tungsten/pn-poly-Si gate CMOS devices with ultra-low resistance of 1 Ω/□ have been demonstrated using Si/TiN buffer layer. Propagation delay time of inverter ring oscillator with this novel gate CMOS is greatly smaller than that with Co-s...
Naohiko Kimizuka, Toyoji Yamamoto, Tohru Mogami
Digest of Technical Papers - Symposium on VLSI Technology   1 Jan 1998   
A new degradation scheme for ultrathin gate dielectric is presented on the basis of gate current. By using Drain Avalanche Hot Carrier (DAHC) injection, we demonstrate for the first time that the hot-carrier induced trap enhances direct-tunneling ...
Takashi Ogura, Toyoji Yamamoto, Yukishige Saito, Yoshihiro Hayashi, Tohru Mogami
Digest of Technical Papers - Symposium on VLSI Technology   1 Jan 1998   
Shallow trench isolation (STI) technology is important to realize high-speed and high-packing-density CMOS-LSIs. A new SiN guard-ring on the upper edge of filled SiO2 for steep-sidewall STI is proposed and evaluated to improve the reverse narrow c...
YAMAMOTO Toyoji, OGURA Takashi, SAITO Yukishige, UWASAWA Ken'ich, TATSUMI Toru, MOGAMI Tohru
半導体・集積回路技術シンポジウム講演論文集   4 Dec 1997   
Hitoshi Wakabayashi, Toyoji Yamamoto, Toru Tatsumi, Ken'ichi Tokunaga, Takao Tamura, Tohru Mogami, Takemitsu Kunio
Technical Digest - International Electron Devices Meeting, IEDM   1 Dec 1997   
High-performance 0.1 μm CMOS devices with elevated salicide film for gate electrode and source/drain (s/D) regions and 80-nm gate side-wall have been demonstrated by a novel silicon selective epitaxial growth (SEG) process. Both junction leakage c...
WAKABAYASHI Hitoshi, ANDOH Takeshi, MOGAMI Tohru, TATSUMI Toru, KUNIO Takemitsu
Extended abstracts of the ... Conference on Solid State Devices and Materials   16 Sep 1997   
Yamamoto Toyoji, Ogura Takashi, Saito Yukishige, Uwasawa Ken'ichi, Tatsumi Toru, Mogami Toru
Technical report of IEICE. SDM   25 Jul 1997   
Ultrathin gate dielectrics are important to realize high performance and low-voltage operation CMOS devices. An advanced ultrathin gate dielectric formation process, that is, direct nitridation of silicon and sequential oxidation, is proposed and ...
Toyoji Yamamoto, Takashi Ogura, Yukishige Saito, Ken&apos;ichi Uwasawa, Toru Tatsumi, Tohru Mogami
Digest of Technical Papers - Symposium on VLSI Technology   1 Jan 1997   
Ultrathin gate dielectrics are important to realize high performance and low-voltage operation CMOS devices. An advanced ultrathin gate dielectric formation process, that is, direct nitridation of silicon and sequential oxidation, is proposed and ...
Hitoshi Wakabayashi, Takeshi Andoh, Kiyoyuki Sato, Kazuyoshi Yoshida, Hidenobu Miyamoto, Tohru Mogami, Takemitsu Kunio
Technical Digest - International Electron Devices Meeting   1 Dec 1996   
A novel W/TiN/pn-poly-Si gate structure has been developed for merged memory and logic LSIs by using sub-quarter micron pn-poly-Si gate CMOS devices. Low-resistance and thermally stable tungsten (W) films were obtained by 5-nm titanium nitride (Ti...
Terada Kazuo, Mogami Toru
Proceedings of the IEICE General Conference   11 Mar 1996   
MOSLSIの高集積化が進むに従い、MOSFET特性の標準偏差を簡単に評価する方法が重要になっている。本研究では、同一構造MOSFETを並列接続したものを1つのMOSFETのように取り扱うことによって、簡単にしきい値電圧の標準偏差を測定する方法を提案し、その実現可能性を調べる。
Toyoji Yamamoto, Akira Tanabe, Mitsuhiro Togo, Akio Furukawa, Tohru Mogami
Digest of Technical Papers - Symposium on VLSI Technology   1 Jan 1996   
This study is carried out to evaluate the high-frequency characteristics of 0.1μm Si-MOSFETs and the influence of parasitic components of fMAX. Reductions of both the gate resistance and junction capacitance are found to be essential to achieve hi...
Ken'ichi Uwasawa, Toyoji Yamamoto, Tohru Mogami
Technical Digest - International Electron Devices Meeting   1 Dec 1995   
A new degradation mode induced by bias temperature (BT) instability is found in short channel p+ polysilicon gate (p+-gate) pMOSFETs. This instability, i.e. negative threshold voltage shift, increases significantly by reducing gate length due to t...
Wakabayashi Hitoshi, Saito Yukishige, Matsuki Takeo, Mogami Tohru, Kunio Takemitsu
Technical report of IEICE. SDM   22 Nov 1995   
In this paper, the Si-surface amorphization effects were evaluated to form the low-resistance titanium silicide (TiSi_2) films for quarter-micron CMOS devices with self-aligned silicide (SALICIDE)process. It was found that the low-resistance TiSi_...
Igura H., Izumikawa M., Furuta K., Ito H., Wakabayashi H., Nakajima K., Mogami T., Horiuchi T., Yamashina M.
Technical report of IEICE. SDM   22 Jun 1995   
A 16-b multiplier-accumulator with stacked CMOS is developed. It can be used for the Digital Signal Processors that are main parts of multimedia portable terminals, and are required to be low-power and high-speed. The stacked-CMOS logic circuit, w...