論文

査読有り
2004年8月

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

IEEE JOURNAL OF SOLID-STATE CIRCUITS
  • H Nosaka
  • E Sano
  • K Ishii
  • M Ida
  • K Kurishima
  • S Yamahata
  • T Shibata
  • H Fukuyama
  • M Yoneyama
  • T Enoki
  • M Muraguchi
  • 全て表示

39
8
開始ページ
1361
終了ページ
1365
記述言語
英語
掲載種別
研究論文(学術雑誌)
DOI
10.1109/JSSC.2004.831463
出版者・発行元
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 2(31)-1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.

リンク情報
DOI
https://doi.org/10.1109/JSSC.2004.831463
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000222902600019&DestApp=WOS_CPL
URL
https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=3843106894&origin=inward
ID情報
  • DOI : 10.1109/JSSC.2004.831463
  • ISSN : 0018-9200
  • eISSN : 1558-173X
  • SCOPUS ID : 3843106894
  • Web of Science ID : WOS:000222902600019

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