徐 祖楽

A 0.79–1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving −232.8-dB FoMref 

IEEE Asian Solid-State Circuits Conference 2021年11月  査読有り

A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with −80-dBc Reference Spur 

IEEE Symposium on VLSI Circuits 2021年6月  査読有り

An All-Standard-Cell-Based Synthesizable SAR ADC with Nonlinearity-Compensated RDAC 

IEEE Transactions on VLSI Systems 2021年  査読有り

A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. 

IEEE Symposium on VLSI Circuits 1-2 2020年  査読有り

Ultralow-Power Class-C Complementary Colpitts Crystal Oscillator 

IEEE Solid-State Circuits Letters 3 274-277 2020年  査読有り

A 3.6GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC 

IEEE Journal of Solid-State Circuits 51(10) 2345-2356 2016年10月  査読有り

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC 

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E98-A(2) 476-484 2015年2月  査読有り