森田行則 (Morita Yukinori) - マイポータル

基本情報

所属: 国立研究開発法人産業技術総合研究所ナノエレクトロニクス研究部門研究グループ長

学位: 博士

研究者番号: 60358190
J-GLOBAL ID: 201801019015861992
researchmap会員ID: B000299963

外部リンク: https://staff.aist.go.jp/y.morita/index.html

https://staff.aist.go.jp/y.morita/index.html

研究キーワード

論文

Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

Yukinori Morita, Koichi Fukuda, Yongxun Liu, Takahiro Mori, Wataru Mizubayashi, Shin-ichi O'uchi, Hiroshi Fuketa, Shintaro Otsuka, Shinji Migita, Meishoku Masahara …

JAPANESE JOURNAL OF APPLIED PHYSICS 56(4) 2017年4月査読有り
Introduction of SiGe/Si heterojunction into novel multilayer tunnel FinFET

Yukinori Morita, Koichi Fukuda, Takahiro Mori, Wataru Mizubayashi, Shinji Migita, Kazuhiko Endo, Shin-ichi O'uchi, Yongxun Liu, Meishoku Masahara, Takashi Matsukawa …

JAPANESE JOURNAL OF APPLIED PHYSICS 55(4) 2016年4月査読有り
Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on performance of tunnel field-effect transistors

Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Koichi Fukuda, Takashi Matsukawa, Kazuhiko Endo, Shin-ichi O'uchi, Yongxun Liu, Meishoku Masahara …

SOLID-STATE ELECTRONICS 113 173-178 2015年11月査読有り
Novel Wafer-Scale Uniform Layer-by-Layer Etching Technology for Line Edge Roughness Reduction and Surface Flattening of 3D Ge Channels

Y. Morita, T. Maeda, H. Ota, W. Mizubayashi, S. O'uchi, M. Masahara, T. Matsukawa, K. Endo

2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 2015年査読有り
Impact of H-2, O-2, and N-2 anneals on atomic-scale surface flattening for 3-D Ge channel architecture

Yukinori Morita, Hiroyuki Ota, Meishoku Masahara, Tatsuro Maeda

2015 SILICON NANOELECTRONICS WORKSHOP (SNW) 2015年査読有り
Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model

Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Akihito Tanabe, Koichi Fukuda, Takashi Matsukawa, Kazuhiko Endo, Shin-ichi O'uchi, Yongxun Liu …

SOLID-STATE ELECTRONICS 102 82-86 2014年12月査読有り
Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect

Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Akihito Tanabe, Koichi Fukuda, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'uchi, Yong Xun Liu …

IEEE ELECTRON DEVICE LETTERS 35(7) 792-794 2014年7月査読有り
Experimental Realization of Complementary p- and n- Tunnel FinFETs with Subthreshold Slopes of less than 60 mV/decade and Very Low (pA/mu m) Off-Current on a Si CMOS Platform

Y. Morita, T. Mori, K. Fukuda, W. Mizubayashi, S. Migita, T. Matsukawa, K. Endo, S. O'uchi, Y. Liu, M. Masahara …

2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 2014年査読有り
Improvement of Epitaxial Channel Quality on Heavily Arsenic-and Boron-doped Si surfaces and Impact on Tunnel FET Performance

Y. Morita, T. Mori, S. Migita, W. Mizubayashi, K. Fukuda, T. Matsukawa, K. Endo, S. O'uchi, Y. X. Liu, M. Masahara …

PROCEEDINGS OF THE 2014 44TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2014) 182-185 2014年査読有り
Two-step annealing effects on ultrathin EOT higher-k (k=40) ALD-FifO(2) gate stacks

Yukinori Morita, Shinji Migita, Wataru Mizubayashi, Meishoku Masahara, Hiroyuki Ota

SOLID-STATE ELECTRONICS 84 58-64 2013年6月査読有り
Tunnel field-effect transistor with epitaxially grown tunnel junction fabricated by source/drain-first and tunnel-junction-last processes

Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Akihito Tanabe, Koichi Fukuda, Meishoku Masahara, Hiroyuki Ota

Japanese Journal of Applied Physics 52(4) 2013年4月査読有り
Performance Limit of Parallel Electric Field Tunnel FET and Improvement by Modified Gate and Channel Configurations

Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. O'uchi, Y. X. Liu …

2013 PROCEEDINGS OF THE EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC) 45-48 2013年査読有り
Simultaneous flattening of Si(110), (111), and (001) surfaces for three-dimensional Si nanowires

Yukinori Morita, Hiroyuki Ota

APPLIED PHYSICS LETTERS 100(26) 2012年6月査読有り
Extremely Scaled (similar to 0.2 nm) Equivalent Oxide Thickness of Higher-k (k=40) HfO2 Gate Stacks Prepared by Atomic Layer Deposition and Oxygen-Controlled Cap Post-Deposition Annealing

Yukinori Morita, Shinji Migita, Wataru Mizubayashi, Hiroyuki Ota

JAPANESE JOURNAL OF APPLIED PHYSICS 51(2) 2012年2月査読有り
Two-step annealing effects on ultrathin EOT higher-k (k 40) ALD-HfO 2 gate stacks

Yukinori Morita, Shinji Migita, Wataru Mizubayashi, Meishoku Masahara, Hiroyuki Ota

European Solid-State Device Research Conference 81-84 2012年査読有り
First Demonstration of Drain Current Enhancement in SOI Tunnel FET with Vertical-Tunnel-Multiplication

Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, M. Masahara, H. Ota

IEEE INTERNATIONAL SOI CONFERENCE 2012年査読有り
Fabrication of Direct-Contact Higher-k HfO2 Gate Stacks by Oxygen-Controlled Cap Post-Deposition Annealing

Yukinori Morita, Shinji Migita, Wataru Mizubayashi, Hiroyuki Ota

JAPANESE JOURNAL OF APPLIED PHYSICS 50(10) 2011年10月査読有り
AFM measurement of atomic-scale Si surface etching by active oxidation

Y. Morita, S. Migita, W. Mizubayashi, H. Ota

SURFACE SCIENCE 604(17-18) 1432-1437 2010年8月査読有り
Impact of Surface Hydrophilicization prior to Atomic Layer Deposition for HfO2/Si Direct-Contact Gate Stacks

Yukinori Morita, Akito Hirano, Shinji Migita, Hiroyuki Ota, Toshihide Nabatame, Akira Toriumi

APPLIED PHYSICS EXPRESS 2(1) 2009年1月査読有り
Surface preparation of Si(001) substrate using low-pH HF solution

Y Morita, M Nishizawa

APPLIED PHYSICS LETTERS 86(17) 2005年4月査読有り

もっとみる

MISC

100

Effect of post-implantation annealing on Al-N isoelectronic trap formation in silicon: Al-N pair formation and defect recovery mechanisms

Takahiro Mori, Yukinori Morita, Takashi Matsukawa

AIP Advances 8(5) 2018年5月1日査読有り
Simulation study of short-channel effects of tunnel field-effect transistors

Koichi Fukuda, Hidehiro Asai, Junichi Hattori, Takahiro Mori, Yukinori Morita, Wataru Mizubayashi, Meishoku Masahara, Shinji Migita, Hiroyuki Ota, Kazuhiro Endo …

Japanese Journal of Applied Physics 57(4) 2018年4月1日査読有り
Epitaxial growth of Ge thin film on Si (001) by DC magnetron sputtering

Shintaro Otsuka, Takahiro Mori, Yukinori Morita, Noriyuki Uchida, Yongxun Liu, Shin-ichi O'uchi, Hiroshi Fuketa, Shinji Migita, Meishoku Masahara, Takashi Matsukawa

MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING 70 3-7 2017年11月査読有り
Impact of residual defects caused by extension ion implantation in FinFETs on parasitic resistance and its fluctuation

Takashi Matsukawa, Yongxun Liu, Takahiro Mori, Yukinori Morita, Shintaro Otsuka, Shin-ichi O'uchi, Hiroshi Fuketa, Shinji Migita, Meishoku Masahara

SOLID-STATE ELECTRONICS 132 103-108 2017年6月査読有り
Bias temperature instability in tunnel field-effect transistors

Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yuki Ishikawa, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Yongxun Liu, Shinichi O'uchi, Junichi Tsukada …

JAPANESE JOURNAL OF APPLIED PHYSICS 56(4) 2017年4月査読有り
On the drain bias dependence of long-channel silicon-on-insulator-based tunnel field-effect transistors

Koichi Fukuda, Takahiro Mori, Hidehiro Asai, Junichi Hattori, Wataru Mizubayashi, Yukinori Morita, Hiroshi Fuketa, Shinji Migita, Hiroyuki Ota, Meishoku Masahara …

JAPANESE JOURNAL OF APPLIED PHYSICS 56(4) 2017年4月査読有り
Structural and electrical characterization of epitaxial Ge thin films on Si(001) formed by sputtering

Shintaro Otsuka, Takahiro Mori, Yukinori Morita, Noriyuki Uchida, Yongxun Liu, Shin-ichi O'uchi, Hiroshi Fuketa, Shinji Migita, Meishoku Masahara, Takashi Matsukawa

JAPANESE JOURNAL OF APPLIED PHYSICS 56(4) 2017年4月査読有り
Suppression of tunneling rate fluctuations in tunnel field-effect transistors by enhancing tunneling probability

Takahiro Mori, Shinji Migita, Koichi Fukuda, Hidehiro Asai, Yukinori Morita, Wataru Mizubayashi, Yongxun Liu, Shin-ichi O'uchi, Hiroshi Fuketa, Shintaro Otsuka …

JAPANESE JOURNAL OF APPLIED PHYSICS 56(4) 2017年4月査読有り
Corrugated Si nanowires with reduced thermal conductivity for wide-temperature-range thermoelectricity

Vladimir Poborchii, Yukinori Morita, Junichi Hattori, Tetsuya Tada, Pavel I. Geshev

JOURNAL OF APPLIED PHYSICS 120(15) 2016年10月査読有り
Impact of extension implantation conditions of fin field-effect transistors on gate-induced drain leakage

Takashi Matsukawa, Yongxun Liu, Takahiro Mori, Yukinori Morita, Shinichi O'uchi, Shintaro Otsuka, Shinji Migita, Meishoku Masahara

JAPANESE JOURNAL OF APPLIED PHYSICS 55(4) 2016年4月査読有り
Closed-form analytical model of static noise margin for ultra-low voltage eight-transistor tunnel FET static random access memory

Hiroshi Fuketa, Shin-ichi O'uchi, Koichi Fukuda, Takahiro Mori, Yukinori Morita, Meishoku Masahara, Takashi Matsukawa

JAPANESE JOURNAL OF APPLIED PHYSICS 55(4) 2016年4月査読有り
Size effects in near-ultraviolet Raman spectra of few-nanometer-thick silicon-on-insulator nanofilms

Vladimir Poborchii, Yukinori Morita, Tetsuya Tada, Pavel I. Geshev, Zhandos N. Utegulov, Alexey Volkov

JOURNAL OF APPLIED PHYSICS 119(15) 2016年4月査読有り
Demonstrating Performance Improvement of Complementary TFET Circuits by ION Enhancement Based on Isoelectronic Trap Technology

T. Mori, H. Asai, J. Hattori, K. Fukuda, S. Otsuka, Y. Morita, S. O'uchi, H. Fuketa, S. Migita, W. Mizubayashi …

2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 2016年査読有り
Floating Gate Type SOI-FinFET Flash Memories with Different Channel Shapes and Interpoly Dielectric Materials

Y. X. Liu, T. Nabatame, T. Matsukawa, K. Endo, S. O'uchi, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, T. Chikyow …

DIELECTRICS FOR NANOSYSTEMS 7: MATERIALS SCIENCE, PROCESSING, RELIABILITY, AND MANUFACTURING 72(2) 11-24 2016年査読有り
Lowering of Effective Work Function Induced by Metal Carbide/HfO2 Interface Dipole for Advanced CMOS

Wataru Mizubayashi, Hiroyuki Ota, Shinji Migita, Yukinori Morita, Kazuhiko Endo

2016 IEEE 16TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) 123-126 2016年査読有り
Highly V-t tunable and low variability triangular fin-channel MOSFETs on SOTB

Y. X. Liu, T. Matsukawa, K. Endo, S. O'uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita …

MICROELECTRONIC ENGINEERING 147 290-293 2015年11月査読有り
Impact of fin length on threshold voltage modulation by back bias for Independent double-gate tunnel fin field-effect transistors

W. Mizubayashi, K. Fukuda, T. Mori, K. Endo, Y. X. Liu, T. Matsukawa, S. O'uchi, Y. Ishikawa, S. Migita, Y. Morita …

SOLID-STATE ELECTRONICS 111 62-66 2015年9月査読有り
Impact of granular work function variation in a gate electrode on low-frequency noise for fin field-effect transistors

Takashi Matsukawa, Koichi Fukuda, Yongxun Liu, Junichi Tsukada, Hiromi Yamauchi, Kazuhiko Endo, Yuki Ishikawa, Shin-ichi O'uchi, Shinji Migita, Yukinori Morita …

APPLIED PHYSICS EXPRESS 8(4) 2015年4月査読有り
Heated ion implantation for high-performance and highly reliable silicon-on-insulator complementary metal-oxide-silicon fin field-effect transistors

Wataru Mizubayashi, Hiroshi Onoda, Yoshiki Nakashima, Yuki Ishikawa, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Shinichi O'uchi, Junichi Tsukada, Hiromi Yamauchi …

JAPANESE JOURNAL OF APPLIED PHYSICS 54(4) 2015年4月査読有り
Channel shape and interpoly dielectric material effects on electrical characteristics of floating-gate-type three-dimensional fin channel flash memories

Yongxun Liu, Toshihide Nabatame, Num Nguyen, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'uchi, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Wataru Mizubayashi …

JAPANESE JOURNAL OF APPLIED PHYSICS 54(4) 2015年4月査読有り

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所属学協会

産業財産権

特許第6284213号相変化チャネルトランジスタ及びその駆動方法。

富永淳二, ポールフォンス, 太田裕之, 森田行則, 右田真司, 伊藤正勝
特開2017-152708 相変化チャネルトランジスタ及びその駆動方法。

富永淳二, ポールフォンス, 太田裕之, 森田行則, 右田真司, 伊藤正勝
特開2016-115686 トンネル電界効果トランジスタ

森田行則, 右田真司, 太田裕之
特許第5910965号トンネル電界効果トランジスタの製造方法及びトンネル電界効果トランジスタ

森田行則
特開2015-159211 トポロジカル相変化論理ゲート及びその駆動方法

伊藤正勝, 森田行則, 富永淳二
特開2015-035478 電界効果トランジスタ

伊藤正勝, 田邊顕人, 森田行則, 太田裕之, 富永淳二
特許第5652926号ゲート絶縁膜の形成方法及び半導体装置の製造方法

森田行則
WO2014-128990 相変化チャネルトランジスタ及びその駆動方法

伊藤正勝, ポールフォンス, 太田裕之, 森田行則, 右田真司, 富永淳二
特許第5565804号ゲートスタック形成方法

森田行則, 右田真司, 太田裕之
特開2013-187291 トンネル電界効果トランジスタの製造方法及びトンネル電界効果トランジスタ

森田行則
特許第5177660号絶縁膜の形成方法

森田行則
WO2012-133433 ゲート絶縁膜の形成方法及び半導体装置の製造方法

森田行則
特開2012-028713 ゲートスタック形成方法

森田行則, 右田真司, 太田裕之
特開2009-239246 絶縁膜の形成方法及び絶縁膜

森田行則
特開2008-311449 シリコンによる2端子抵抗スイッチ素子及び半導体デバイス

内藤泰久, 森田行則, 堀川昌代, 清水哲夫
特許第4085162号シリコン基板の表面処理方法

森田行則, 西澤正泰
特開2005-142445 シリコン基板の表面処理方法

森田行則, 西澤正泰
特許第3517677号窒化シリコン単分子層膜の形成方法

森田行則, 石田敬雄, 徳本洋志
特開2002-217192 窒化シリコン単分子層膜の形成方法

森田行則, 石田敬雄, 徳本洋志
特開2000-067799 微細パターン形成方法

森田行則, 徳本洋志

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