論文

査読有り 筆頭著者
2015年9月28日

On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck

Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015
  • Ryota Yasudo
  • ,
  • Hiroki Matsutani
  • ,
  • Michihiro Koibuchi
  • ,
  • Hideharu Amano
  • ,
  • Tadao Nakamura

開始ページ
16:1-16:8
終了ページ
記述言語
英語
掲載種別
研究論文(国際会議プロシーディングス)
DOI
10.1145/2786572.2786583
出版者・発行元
Association for Computing Machinery, Inc

Technology scaling makes designers face difficulties dealing with wire delay of long global interconnects, especially for high-radix networks. In this context, we propose decentralization of on-chip packet routers. A decentralized router consists of submodules, each of which has particular functionality and they are scattered on a link, thereby long wires are segmented. Our starting point is from a conventional router architecture, and we illustrate four case studies to generalize our proposal. We also propose a new buffer design and how to balance pipelines of a router. A proof-of-concept is shown in 28-nm process technology. Our results demonstrate that the decentralization of an on-chip router enables Link Traversal (LT) stages to be eliminated, and the critical path delay is improved by up to 45% with the reduced area compared with a conventional router. As technology advances, the benefit of the decentralized routers become more substantial in the nano-scale era.

リンク情報
DOI
https://doi.org/10.1145/2786572.2786583
DBLP
https://dblp.uni-trier.de/rec/conf/nocs/YasudoMKAN15
URL
http://dblp.uni-trier.de/db/conf/nocs/nocs2015.html#conf/nocs/YasudoMKAN15
ID情報
  • DOI : 10.1145/2786572.2786583
  • DBLP ID : conf/nocs/YasudoMKAN15
  • SCOPUS ID : 84984623441

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