Tomohiro Yoneda

Profile Information

Affiliation: National Institute of Informatics Information Systems Architecture Science Research Division Professor
: 総合研究大学院大学複合科学研究科情報学専攻教授

210

Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices

T. Yoneda, M. Imai

Proc. of ASYNC2020 102 - 110 May, 2020 Peer-reviewed
Hardware Trojan Insertion and Detection in Asynchronous Circuits

Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai

Proc. of ASYNC2019 134 - 143 May, 2019 Peer-reviewed
MTJ-based asynchronous circuits for Re-initialization free computing against power failures

N. Onizawa, M. Imai, T. Yoneda, T. Hanyu

Microelectronics Journal 82 46 - 61 Dec, 2018 Peer-reviewed
Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols

Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda

Proc. of ASYNC2018 1 - 8 May, 2018 Peer-reviewed
Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing

M. Imai, N. Onizawa, T. Hanyu, T. Yoneda

Proc. of SASIMI2018 283 - 288 Mar, 2018 Peer-reviewed

Study of a Simplified Digital Spiking Neuron and Its FPGA Implementation

Tomohiro Yoneda

RECONF2019-65 135 - 140 Jan, 2020
An Idea of SPF File Reduction for Post-Layout Simulations

Tomohiro Yoneda

Proc. of DA Symposium 2019 DAS2019 166 - 171 Aug, 2019 Peer-reviewed
多数決イネーブルラッチを用いた非同期式回路の耐故障性に関する一検討

今井雅, 米田友洋

電子情報通信学会技術研究報告 VLD2016-39 179 - 184 Jun, 2016
DTTR方式によるマルチコアシステム向けのタスクの最大並列度を基にしたタスク割り当て手法

齋藤寛, 今井雅, 米田友洋

電子情報通信学会技術研究報告 Vol. 115(465) 13 - 18 Feb, 2016
DTTR 方式によるマルチコアシステムの信頼性向上のためのタスク割り当て手法の検討

齊藤寛, 今井雅, 米田友洋

情報処理学会研究報告 Vol. 2015-SLDM-172(12) 63 - 68 Oct, 2015