2014年
Multiple-Clock Multiple-Edge-Triggered Multiple-Bit Flip-flops for Two-Phase Handshaking Asynchronous Circuits
2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
- ,
- 開始ページ
- 141
- 終了ページ
- 144
- 記述言語
- 英語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- DOI
- 10.1109/ISCAS.2014.6865085
- 出版者・発行元
- IEEE
This paper proposes multiple-clock multiple-edge-triggered multiple-bit flip-flops for designing simple and straightforward asynchronous control circuits of the two-phase handshaking protocol. The proposed flip-flops have multiple clocks and multiple data inputs, and each data input can be stored in the flip-flop at both the rising edge and the falling edge of the corresponding clock. They can be applied in the asynchronous design of the two-phase handshaking protocol not only for synthesizing simple control circuits, but also for obtaining robust circuits. The performance of the proposed flip-flops have been evaluated using the PTM 22nm HP device parameters.
- リンク情報
- ID情報
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- DOI : 10.1109/ISCAS.2014.6865085
- ISSN : 0271-4302
- Web of Science ID : WOS:000346488600034