2016年
Introduction of Atomically Flattening of Si Surface to Large-Scale Integration Process Employing Shallow Trench Isolation
ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY
- 巻
- 5
- 号
- 2
- 開始ページ
- P67
- 終了ページ
- P72
- 記述言語
- 英語
- 掲載種別
- 研究論文(学術雑誌)
- DOI
- 10.1149/2.0221602jss
- 出版者・発行元
- ELECTROCHEMICAL SOC INC
Atomically flattening technology was introduced to the widely used complementary metal oxide silicon process employing sallow trench isolation at the 0.22-mu m technology node. Two methods were investigated. The first method is to apply the atomically flattening to the starting Si wafer, and the second method is to apply this just before forming the gate oxide. In both methods, atomically flat gate insulator/Si interface could be obtained, and the test array circuit for evaluating the electrical characteristics of many (>130,000) metal oxide semiconductor field effect transistors was successfully fabricated on an entire 200-mm-diameter wafer. By evaluating the test circuit, the noise amplitude of the gate-source voltage related to the random telegraph noise was reduced owing to introducing the atomically flat gate insulator/Si interface. The charge-to-breakdown of the gate oxide was also improved. (C) 2015 The Electrochemical Society. All rights reserved.
- リンク情報
- ID情報
-
- DOI : 10.1149/2.0221602jss
- ISSN : 2162-8769
- eISSN : 2162-8777
- Web of Science ID : WOS:000365748800004