2011年10月
Evaluation for Anomalous Stress-Induced Leakage Current of Gate SiO2 Films Using Array Test Pattern
IEEE TRANSACTIONS ON ELECTRON DEVICES
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- 巻
- 58
- 号
- 10
- 開始ページ
- 3307
- 終了ページ
- 3313
- 記述言語
- 英語
- 掲載種別
- 研究論文(学術雑誌)
- DOI
- 10.1109/TED.2011.2161991
- 出版者・発行元
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Using the array test pattern, gate current through the tunnel oxide on the order of 10(-16) A can be measured for about 1 000 000 transistors within 4 min. Because this test pattern can be fabricated by simple processes and its peripheral circuits are simple structures, the tunnel dielectric formation method and condition can be changed drastically. It was found that anomalous stress-induced leakage current (SILC) appears or disappears by applying electrical stress, and it is annealed out during a relatively high temperature measurement at 60 degrees C. Random telegraph signal in SILC can be observed in some transistors. These are very similar phenomena observed in Flash memory cells. We consider that, using this test pattern for the development of tunnel oxide, we can clarify the origin of anomalous SILC and promote the downscaling of tunnel oxide thickness.
- リンク情報
- ID情報
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- DOI : 10.1109/TED.2011.2161991
- ISSN : 0018-9383
- eISSN : 1557-9646
- Web of Science ID : WOS:000295100300011