Yukinori Sato

Profile Information

Affiliation: Graduate School of Engineering Department of Computer Science and Engineering, Toyohashi University of Technology

Researcher number: 30452113
ORCID ID: https://orcid.org/0000-0002-3491-1692
J-GLOBAL ID: 200901087974214977
researchmap Member ID: 5000066403

External link: https://perf.cs.tut.ac.jp/~yukinori/

Research Interests

Research Areas

Informatics / Computer systems / Hardware/Software Co-design

Research History

Aug, 2022 - Present

Visiting scientist, RCCS, RIKEN
2018 - Present

Associate Professor, Department of Computer Science and Engineering, Tohoyashi University of Technology
Nov, 2021 - Mar, 2022

Visiting scientist, Processor Research Team, Center for Computational Science (R-CCS), RIKEN
Oct, 2018 - Mar, 2022

PRESTO researcher, Japan Science and Technology Agency
2015 - 2018

Specially Appointed Associate Professor (Lecturer), Tokyo Institute of Technology Global Scientific Information and Computing Center
2007 - 2015

Assistant Professor, Center for Information Science, Japan Advanced Institute of Science and Technology

Education

Major Committee Memberships

May, 2016 - May, 2022

Registration Co-Chair, IEEE Symposium on Low-Power and High-Speed Chips and Sysems (COOL Chips)
Jun, 2016 - Jun, 2020

Associate Editor, IEICE Transactions on Information and Systems
Mar, 2019 - Nov, 2019

Steering committee member, ACM SINGPLAN International Workshop on AI-Inspired and Empirical Methods for Software Engineering on Parallel Computing Systems
Jun, 2018 - May, 2019

Guest Editor. Special Section on Reconfigurable Systems. (May 2020 Issue), IEICE Transactions on Information and Systems.

Awards

Nov, 2021

Best Paper Award, "Thread-Aware Cache Simulator for HPC Application Tuning", 12th International Workshop on Advances in Networking and Computing (WANC2021)

Kazuki Chugo, Yukinori Sato
Nov, 2021

Best Paper Award, "A simulation of a memory subsystem using a highly energy-efficient but erroneous MRAM", 9th International Workshop on Computer Systems and Architectures (CSA2021)

Daiki Saito, Takahiro Hirofuchi, Hiroko Arai, Yukinori Sato
Apr, 2021

Featured Poster Award, "An Online Trace-Driven Cache Simulator for ARM-Based Supercomputers", IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 24), 2021

Kazuki Chugo, Yukinori Sato
Jun, 2020

Service Award for the contribution of editorial expertise toward “IEICE Transactions on Information and Systems", IEICE

Major Papers

Thread-Aware Cache Simulator for HPC Application Tuning

Kazuki Chugo, Yukinori Sato

2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW), 424-428, Nov, 2021 Peer-reviewedLast author
A simulation of a memory subsystem using a highly energy-efficient but erroneous MRAM

Daiki Saito, Takahiro Hirofuchi, Hiroko Arai, Yukinori Sato

2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW), 120-126, Nov, 2021 Peer-reviewedLast author
Hodgkin-Huxley-Based Efficient Neural Simulation with Networks Connecting to Near-Neighbor Neurons

Masashi Ogaki, Yukinori Sato

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2021)., 109-116, Jul, 2021 Peer-reviewedLast authorCorresponding author
An autotuning framework for scalable execution of tiled code via iterative polyhedral compilation

Yukinori Sato, Tomoya Yuki, Toshio Endo

ACM Transactions on Architecture and Code Optimization, 15(4) 67:01:00-67:23:00, 2019 Peer-reviewed
An accurate simulator of cache-line conflicts to exploit the underlying cache performance

Yukinori Sato, Tomoya Yuki, Toshio Endo

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 10417 LNCS 119-133, Aug, 2017 Peer-reviewedLead author
ExanaDBT: A dynamic compilation system for transparent polyhedral optimizations at runtime

Yukinori Sato, Tomoya Yuki, Toshio Endo

ACM International Conference on Computing Frontiers 2017, CF 2017, 191-200, May 15, 2017 Peer-reviewed
Identifying program loop nesting structures during execution of machine code

Sato, Y., Inoguchi, Y., Nakamura, T.

IEICE Transactions on Information and Systems, E97-D(9) 2371-2385, 2014 Peer-reviewed
Whole program data dependence profiling to unveil parallel regions in the dynamic execution

Yukinori Sato, Yasushi Inoguchi, Tadao Nakamura

Proceedings - 2012 IEEE International Symposium on Workload Characterization, IISWC 2012, 69-80, 2012 Peer-reviewed
Evaluating Reconfigurable Dataflow Computing Using the Himeno Benchmark

Yukinori Sato, Yasushi Inoguchi, Wayne Luk, Tadao Nakamura

2012 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 1-7, 2012 Peer-reviewed
On-the-fly Detection of Precise Loop Nests across Procedures on a Dynamic Binary Translation System

Yukinori Sato, Yasushi Inoguchi, Tadao Nakamura

PROCEEDINGS OF THE 2011 8TH ACM INTERNATIONAL CONFERENCE ON COMPUTING FRONTIERS (CF 2011), 25, May, 2011 Peer-reviewed

Misc.

技術展示 CPU性能チューニングを支援するアプリケーション解析ツールExanaのデモ

佐藤幸紀, 佐藤真平, 遠藤敏夫

電子情報通信学会技術研究報告コンピュータシステム, 11-13, Oct, 2015
A Scalable Processor for Real-time Sound Rendering.

Tan Yiyu, Yasushi Inoguchi, Yukinori Sato, Yukio Iwaya, Makoto Otani, TakaoTsuchiya

Proceedings of IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII). April, 2015., 1-2, 2015 Peer-reviewed
メモリ階層性能シミュレータを用いたCPU 単体性能チューニング

佐藤幸紀, 佐藤真平

ハイパフォーマンスコンピューティングと計算科学シンポジウム2015(HPCS 2015) 論文集, (2015) 100-100, 2015 Peer-reviewed
メモリ階層の深化に対応するメモリアクセス解析ツール

松原裕貴, 佐藤幸紀

ハイパフォーマンスコンピューティングと計算科学シンポジウム論文集, 2014(2014) 45-45, Dec 31, 2013
2P2-14 A Real-time Sound Rendering System based on the Finite-Difference Time-Domain Algorithm(Poster Session)

Yiyu Tan, Inoguchi Yasushi, Sato Yukinori, Otani Makoto, Iwaya Yukio, Matsuoka Hiroshi, Tsuchiya Takao

Proceedings of Symposium on Ultrasonic Electronics, 34 235-236, Nov 20, 2013
A Low Power Oriented Design Framework for Considering Reconfiguration Time on Embedded Systems

ARAKI Koichi, SATO Yukinori, INOGUCHI Yasushi

IEICE technical report, 113(221) 67-72, Sep 18, 2013
JAISTにおける共有計算サーバ環境 (北陸先端科学技術大学院大学共有計算サーバ使用成果報告2012)

佐藤幸紀

Technical memorandum, 2013(1) 4-7, Jul 25, 2013
北陸先端科学技術大学院大学共有計算サーバ使用成果報告2012

佐藤幸紀, 尾崎泰助

Technical memorandum, 2013(1) 1-58, Jul 25, 2013
バイナリ変換による透過的なループ構造解析とコード実行時の区間実行時間の計測

佐藤幸紀

情報処理学会研究報告. [ハイパフォーマンスコンピューティング], 2013(3) 1-8, Jul 24, 2013
メモリトレース解析によるアクセスパターンのモデル化

松原裕貴, 佐藤幸紀

情報処理学会研究報告. [ハイパフォーマンスコンピューティング], 2013(45) 1-6, Jul 24, 2013
JAISTにおける共有計算サーバ環境 (北陸先端科学技術大学院大学共有計算サーバ使用成果報告2011)

佐藤幸紀, 尾崎泰助 [編]

Technical memorandum, 2012(1) 4-7, Jul 3, 2012
Runtime data flow analysis among loop iterations using a binary translation system

2012(11) 1-8, Mar 19, 2012
A Design Framework for relieving a HW Bottleneck on FPGAs Connected with a High-Speed Data Bus

ARAKI Koichi, SATO Yukinori, INOGUCHI Yasushi

IEICE technical report, 111(218) 63-68, Sep 19, 2011
北陸先端科学技術大学院大学共有計算サーバ使用成果報告2010

尾崎泰助, 佐藤幸紀

Technical memorandum, 2011(1) 1-61,巻頭1p, Aug 2, 2011
Runtime data flow analysis using Loop-Call Context Tree

2011(13) 1-6, Jul 20, 2011
Detecting nested loop structures using a dynamic binary translator and its application to performance tuning

2010(10) 1-7, Dec 9, 2010
An Effective Processing Method for Parallel Loops on FPGA with PCI-Express

ARAKI Koichi, SATO Yukinori, INOGUCHI Yasushi

IEICE technical report, 110(319) 49-54, Nov 23, 2010
省電力ネットワークを実現するためのL2スイッチ電力消費特性

西澤良太, 佐藤幸紀, 井口寧

E-48, Sep 11, 2010
JAISTにおける共有計算サーバ環境 (北陸先端科学技術大学院大学共有計算サーバ使用成果報告2009)

佐藤幸紀, 太田理

Technical memorandum, 2010(1) 4-7, Jul 27, 2010
北陸先端科学技術大学院大学共有計算サーバ使用成果報告2009

太田理, 尾崎泰助, 佐藤幸紀

Technical memorandum, 2010(1) 1-43,巻頭1p, Jul 27, 2010

Books and Other Publications

White Paper on Next-Generation Advanced Computing Infrastructure

(Role: Contributor)

Nov, 2020
Software Technology That Deals with Deeper Memory Hierarchy in Post-petascale Era.

Toshio Endo, HIroko Midorikawa, Yukinori Sato (Role: Joint author, Chapter 12, Advanced Software Technologies for Post-Peta Scale Computing.)

Springer, Jan 1, 2019
AI-SEPS 2018: Proceedings of the 5th ACM SIGPLAN International Workshop on Artificial Intelligence and Empirical Methods for Software Engineering and Parallel Computing Systems

Pablo de Oliveira Castro, Ali Jannesari, Yukinori Sato, Michael Ringenburg (Role: Joint editor)

ACM, Nov 1, 2018
SEPS 2017: Proceedings of the 4th ACM SIGPLAN International Workshop on Software Engineering for Parallel Systems,

Ali Jannesari, Pablo de Oliveira Castro, Yukinori Sato, Tim Mattson (Role: Joint editor)

ACM, Nov 1, 2017
SEPS 2016: Proceedings of the 3rd International Workshop on Software Engineering for Parallel Systems

Ali Jannesari, Yukinori Sato, Stefan Winter (Role: Joint editor)

ACM, Nov 1, 2016
Workshop Preview of the 2nd International Workshop on Software for Parallel Systems (SEPS 2015)

Ali Jannesari, Siegfried Benkner, Xinghui Zhao, Ehsan Atoofian, Yukinori Sato (Role: Joint author)

ACM, Nov 1, 2015
HPC Systems at JAIST and Development of Dynamic Loop Monitoring Tools Toward Runtime Parallelization

Yukinori Sato

Springer, Oct 1, 2011

Major Presentations

Hodgkin-Huxley-Based Efficient Neural Simulation with Networks Connecting to Near-Neighbor Neurons

Masashi Ogaki, Yukinori Sato

In the 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2021)., Jul 8, 2021

Professional Memberships

Works

PATT: Polyhedral compilation-based AuTo Tile size optimizer

SATO Yukinori

Nov, 2018 - Present Software
Exana/ExanaDBT/Exana-C2Sim

SATO Yukinori

Dec 5, 2016 - Apr 13, 2020 Software

Research Projects

Automatic synthesis of memory access optimization programs synergistically coordinated with deep learning and empirical methods

Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C), Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, Apr, 2019 - Mar, 2023
High-level optimization of memory references for productive and efficient development of FPGA accelerators

Grants-in-Aid for Scientific Research Grant-in-Aid for Young Scientists (B), Grant-in-Aid for Young Scientists (B), Japan Society for the Promotion of Science, Apr, 2017 - Mar, 2020

Sato Yukinori
Development of data-driven custom pipeline processing system for accelerating big data processing

Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research, Grant-in-Aid for Challenging Exploratory Research, Japan Society for the Promotion of Science, Apr, 2014 - Mar, 2018

Sato Yukinori
Checkpoint restart technologies for hierarchcal storages

Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research, Grant-in-Aid for Challenging Exploratory Research, Japan Society for the Promotion of Science, Apr, 2014 - Mar, 2016

Hiroyuki Takizawa, Uno Atsuya, Kobayashi Hiroaki, Egawa Ryusuke, Sato Yukinori
Ultra High Speed Audio Fingerprint Detection and Search

Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B), Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, Apr, 2012 - Mar, 2015

INOGUCHI Yasushi, FUKUSHI Masaru, KANEKO Mineo, SATOU Yukinori
Designing a Practical Processing Model of Parallel Instructions Using Real-time Dependence Analysis

Grants-in-Aid for Scientific Research Grant-in-Aid for Young Scientists (B), Grant-in-Aid for Young Scientists (B), Japan Society for the Promotion of Science, 2009 - 2011

SATO Yukinori
High speed audio fingerprint detection to support fair trade of digital contents and real time search.

Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C), Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, 2008 - 2010

INOGUCHI Yasushi, SATO Yukinori, FUKUSHI Masaru
Study on Hardware-Software Collaborative Scheduling for Highly Efficient Multithreading

Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B), Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2006 - 2009

KOBAYASHI Hiroaki, NAKAMURA Tadao, SUZUKI Kenichi, TAKIZAWA Hiroyuki, EGAWA Ryusuke, SATO Yukinori, KOTERA Isao, FUNAYA Yusuke, SATO Masayuki
Effective execution of instruction sequences
命令列の効率的実行に関する研究

Industrial Property Rights

特願特願2022-037139 演算処理装置および演算処理方法

佐藤幸紀

Media Coverage

最新脳科学と応用(2) ～脳の情報処理アーキテクチャ～

Yano E plus 2023年1月号, 4-4．国立大学法人豊橋技術科学大学（60～64ページ）, Jan, 2023

Profile Information

Research Interests

Research Areas

Research History

Education

Major Committee Memberships

Awards

Major Papers

Misc.

Books and Other Publications

Major Presentations

Professional Memberships

Works

Research Projects

Industrial Property Rights

Media Coverage

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