2015年
Analyzing and Mitigating the Impact of Manufacturing Variability in Power-Constrained Supercomputing
PROCEEDINGS OF SC15: THE INTERNATIONAL CONFERENCE FOR HIGH PERFORMANCE COMPUTING, NETWORKING, STORAGE AND ANALYSIS
- 開始ページ
- 78:1-78:12
- 終了ページ
- 記述言語
- 英語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- DOI
- 10.1145/2807591.2807638
- 出版者・発行元
- ASSOC COMPUTING MACHINERY
A key challenge in next-generation supercomputing is to effectively schedule limited power resources. Modern processors suffer from increasingly large power variations due to the chip manufacturing process. These variations lead to power inhomogeneity in current systems and manifest into performance inhomogeneity in power constrained environments, drastically limiting supercomputing performance. We present a first-of-its-kind study on manufacturing variability on four production HPC systems spanning four microarchitectures, analyze its impact on HPC applications, and propose a novel variation-aware power budgeting scheme to maximize effective application performance. Our low-cost and scalable budgeting algorithm strives to achieve performance homogeneity under a power constraint by deriving application-specific, module-level power allocations. Experimental results using a 1,920 socket system show up to 5.4X speedup, with an average speedup of 1.8X across all benchmarks when compared to a variation-unaware power allocation scheme.
- リンク情報
-
- DOI
- https://doi.org/10.1145/2807591.2807638
- DBLP
- https://dblp.uni-trier.de/rec/conf/sc/InadomiPIARSLWF15
- Web of Science
- https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000382162500079&DestApp=WOS_CPL
- URL
- http://dblp.uni-trier.de/db/conf/sc/sc2015.html#conf/sc/InadomiPIARSLWF15
- ID情報
-
- DOI : 10.1145/2807591.2807638
- DBLP ID : conf/sc/InadomiPIARSLWF15
- Web of Science ID : WOS:000382162500079