Soft error jeopardizes the reliability of semiconductor devices, especially those working at low voltage. In recent years, silicon-on-thin-box (SOTB), which is a FD-SOI device, is drawing attention since it is suitable for ultra-low-voltage operation. This work evaluates the contributions of SRAM, FF and combinational circuit to chip-level soft error rate (SER) based on irradiation test results. For this evaluation, this work performed neutron irradiation test for characterizing single event transient (SET) rate of SOTB and bulk circuits at 0.5V. Combining previously reported SRAM and FF error rates with the measured SET rate, we estimated chip-level SER and each contributionto chip-level SER for embedded and high-performance processors. For both the processors, 99% errors occur at SRAM in both SOTB and bulk chips at 0.5 and 1.0V, and the overall chip-level SERs of the assumed SOTB chip at 0.5V is at least 10× lower than that of bulk chip. On the other hand, when ECC is applied to SRAM in the SOTB chip, MCUs occurring at SRAM are dominant in the embedded processor while SEUs at FFs are not negligible.