Recently, many studies of field programmable gate array (FPGA) hardware accelerators have been reported, in addition to studies of general-purpose computing on graphics processing units (GPGPUs), Xeon Phi, and so on. Since parallel processing is indispensable for such accelerating applications on FPGAs, implementing numerous parallel processing circuits is important to improve the performance of such FPGA hardware accelerators. When implementing a parallel operation for a conventional FPGA, some waste occurs: the same context is stored on numerous regions of configuration memory. This waste presents a critical issue because FPGAs used as accelerators perform parallel processing exclusively in most cases. This paper therefore proposes a parallel-operation-oriented FPGA exploiting a common configuration context. Herein, we describe the advantages of gate density, propagation delay, and compilation time in parallel-operation-oriented FPGAs.