Papers

Peer-reviewed
Dec, 2013

FPGA Blokus Duo Solver using a massively parallel architecture

PROCEEDINGS OF THE 2013 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT)
  • Takashi Yoza
  • Retsu Moriwaki
  • Yuki Torigai
  • Yuki Kamikubo
  • Takayuki Kubota
  • Takahiro Watanabe
  • Takumi Fujimori
  • Hiroyuki Ito
  • Masato Seo
  • Kouta Akagi
  • Yuichiro Yamaji
  • Minoru Watanabe
  • Display all

First page
494
Last page
497
Language
English
Publishing type
Research paper (international conference proceedings)
DOI
10.1109/FPT.2013.6718426
Publisher
IEEE

Recently, many game programs have been developed aggressively as hardware on field programmable gate arrays (FPGAs) because of the extremely large solution space of such games as the Connect6 game, Blokus Duo game, and others so that the computational capabilities of computers are currently insufficient to search all possible solutions. This report describes an FPGA acceleration experiment for the Blokus Duo game. The FPGA Blokus Duo Solver was implemented on an Arria II GX FPGA (Altera Corp.). Its operation speed is 25 times faster than C++ based software operation of the same algorithm on a Core i7 processor.

Link information
DOI
https://doi.org/10.1109/FPT.2013.6718426
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000342561900086&DestApp=WOS_CPL
ID information
  • DOI : 10.1109/FPT.2013.6718426
  • Web of Science ID : WOS:000342561900086

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