The temperature dependence of the variability of drain-induced barrier lowering (DIBL) and subthreshold slope (SS) is experimentally investigated in bulk and fully depleted silicon-on-thin-buried-oxide MOSFETs. Measurement results show that variability of both DIBL and SS is reduced at high temperature. The origins of these new findings are explained and confirmed by device simulations. It is found that reduced variability of DIBL at high temperature originates from randomness along the channel length direction (source-drain asymmetry), while reduced variability of SS at high temperature is mainly influenced by randomness along the channel width direction. (C) 2019 The Japan Society of Applied Physics