2017年3月
Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
- ,
- ,
- 巻
- E100D
- 号
- 3
- 開始ページ
- 531
- 終了ページ
- 536
- 記述言語
- 英語
- 掲載種別
- 研究論文(学術雑誌)
- DOI
- 10.1587/transinf.2016EDP7158
- 出版者・発行元
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
A floating-point multiplier with concurrent error detection capability by partial duplication is proposed. It uses a truncated multiplier for checking of the significand (mantissa) multiplication instead of full duplication. The proposed multiplier can detect any erroneous output with error larger than one unit in the last place (1 ulp) of the significand, which may be overlooked by residue checking. Its circuit area is smaller than that of a fully duplicated one. Area overhead of a single-precision multiplier is about 78% and that of a double-precision one is about 65%.
- リンク情報
- ID情報
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- DOI : 10.1587/transinf.2016EDP7158
- ISSN : 1745-1361
- Web of Science ID : WOS:000399371000014