This paper proposes a square root hardware algorithm using the redundant binary representation in the internal computation. A discussion is made for the realization of a combinational square‐rooter based on the algorithm. This paper considers the computation of the mantissa in square‐rooting for the binary normalized floating‐point representation. The proposed algorithm is a kind of subtract‐and‐shift square‐root method. Partial remainders are represented by the redundant binary representation, where each digit is an element of {‐1, 0, 1}. Then each digit of the square root is determined from {‐1, 0, 1}, by examining the upper three digits of the partial remainder. The computation for the partial remainder is affected in the redundant binary number system. Finally, the square root determined in the redundant binary representation is converted into the ordinary binary representation. In the redundant binary representation, the addition of two numbers can be effected without carry propagation. Consequently, by using the combinational circuit, each digit of the square root can be determined in a constant time, independently of the number of digits of the operand. The computation time for the n‐bit square rooter (number of stages) is proportional to n. The number of logic elements in the circuit is proportional to n2. The hardware structure is a regular cellular array, which is suited for VLSI implementation. When the circuit is implemented on a VLSI chip, the chip is proportional to n2. The proposed square rooter has nearly the same circuit structure and the hardware complexity, compared with the conventional subtract‐and‐shift square rooter using ripple carry adder. The computation time is approximately one‐fifth for 32‐bit and one‐tenth for 64‐bit, compared with earlier circuits. Copyright © 1986 Wiley Periodicals, Inc., A Wiley Company