We have designed a reconfigurable data-path (RDP) prototype based on the single-flux-quantum (SFQ) circuit. The RDP serves as an accelerator for a high performance computer and is composed of many stages of the array of floating point number processing units (FPUs) connected by reconfigurable operand routing networks (ORNs). The FPU array usually includes shift-registers (SRs) in order that the data is forwarded to the next stage without calculation. The data-path is reconfigured so as to reflect a long repeat instruction appearing in large-scale calculations. We can implement parallel and pipelined processing without memory access in such calculations, reducing the required bandwidth between a memory and a microprocessor. The SFQ high speed network switches and bit-serial/ slice FPUs realize reduction in the circuit areas and in the power consumption compared to semiconductor devices when we make up the RDP by using the SFQ circuit. As a first step of the development of the SFQ-RDP, we design a 2 x 2 RDP prototype composed of double arrays of dual arithmetic logic units (ALUs). The prototype also has dual SRs in each array and four ORNs. We use bit-serial ALUs designed to operate at 25 GHz. Each ORN behaves like a 4 x 2 crossbar switch. We have demonstrated the reconfiguration in the RDP prototype made up of 15 050 Josephson junctions though only some of the functions of ALUs are available.