MISC

2005年12月

An incremental placement algorithm for building block layout design based on the O-tree representation

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
  • J Li
  • ,
  • JB Yu
  • ,
  • H Miyashita

E88A
12
開始ページ
3398
終了ページ
3404
記述言語
英語
掲載種別
DOI
10.1093/ietfec/e88-a.12.3398
出版者・発行元
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

Incremental modification and optimization in VLSI physical design is of fundamental importance. Based on the O-tree (ordered tree) representation which has more prominent advantages in comparison with other topological representations of non-slicing floorplans, in this paper, we present an incremental placement algorithm for BBL (Building Block Layout) design in VLSI physical design. The good performance of experimental results in dealing with some instances proves the effectiveness of our algorithm.

リンク情報
DOI
https://doi.org/10.1093/ietfec/e88-a.12.3398
CiNii Articles
http://ci.nii.ac.jp/naid/110004019442
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000234281300017&DestApp=WOS_CPL
ID情報
  • DOI : 10.1093/ietfec/e88-a.12.3398
  • ISSN : 0916-8508
  • eISSN : 1745-1337
  • CiNii Articles ID : 110004019442
  • Web of Science ID : WOS:000234281300017

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